1. Introduction In this lab, we are going to study the basic sequential logic circuit (J-K Flip-flop, D Flip-flop and T

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1 Introduction In This Lab We Are Going To Study The Basic Sequential Logic Circuit J K Flip Flop D Flip Flop And T 1 (30.43 KiB) Viewed 51 times

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1. Introduction In this lab, we are going to study the basic sequential logic circuit (J-K Flip-flop, D Flip-flop and T Flip- flop). Especially, we are going to study how to convert from one type of FF to the other type. We are going to evaluate its functionality using the OrCAD and PSpice. 2. Logic components 7408 (Quad 2-input AND gate), 7432 (Quad 2-input OR gate), 7404 (Hex Inverter), 7474 (Dual D Flip-Flop). 7476 (Dual J-K Flip-Flop) 3. Familiarization of J-K Flip-flop • Consult the attached data sheet of IC 74LS76A (shown in Appendix), which offers individual J, K, Clock Pulse, Direct Set/Preset and Direct Clear inputs. • Use no more than one sentence to describe the functions of the following pins: , к CP So , Ср
4.1 4. Conversion of Flip-flops Conversion of a J-K flip-flop to a D-type flip-flop: Design and simulate a D-type flip-flop from a J-K flip-flop with logic gates, and verify your design by going through the following truth table, where On = Output at time n and Qu+1 = Output at time n+1. Input Output Active? D 0(t+1) Q'(t+1) 0 0 Q0 Q'0) 0 0 1 1 0 0 1 1 1 1 0 The test stimuli can be generated by defining the following signal timings as follows, CP (CLK) D PRE NCER Stimulus: Signal: COMMAND1 Ons 0 Ons 0 Ons 1 Ons 0 COMMAND2 100ns 1 250ns 1 50ns 1 50ns 1 COMMANDS 200ns 0 350ns 0 950ns 0 750ns 0 COMMAND4 300ns 1 550ns 1 1050ns 1 850ns 1 COMMANDS 400ns 0 650ns 0 COMMANDE 500ns 1 600ns 0 COMMANDY COMMANDS 700ns 1 where. CLK-Clock signal input to the flip-flop D-D signal input to the flip-flop nPRE - Direct Set/Preset input to the flip-flop CLR - Direct Clear input to the flip-flop consider using DigClock instead of hardcoding the STIMI source, like the lecture demo.