Analog VLSI-Laboratory Laboratory #5: Analysis and Design of Single-Stage Amplifier Objective: To understand the fundame

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Analog Vlsi Laboratory Laboratory 5 Analysis And Design Of Single Stage Amplifier Objective To Understand The Fundame 1 (95.42 KiB) Viewed 38 times

Analog VLSI-Laboratory Laboratory #5: Analysis and Design of Single-Stage Amplifier Objective: To understand the fundamental operation of single stage amplifier and design the common source amplifier with resistive load. Several figure of merits are discussed with the single stage amplifier designed in LTSpice. Task 1: Construct the common source amplifier with given schematic below avdd V2 R1 1k 3.5 vout C1 1p M1 TestN vin V1 .model TestN nmos (kp=90u vt0=0.7 lambda=0.1) SINE(1.2) AC 10 .ac dec 21 1k 1G ;.op Figure 1. Schematic: common source amplifier with resistive load The schematic given here has the following dimensions and designs. NMOS M3: L=1um, W=100um Gate dc bias: 1.2V Load resistance: 1 kohms 1. DC analysis Run the DC analysis and find the operating point for trans-conductance device (M1). 1.1. Hand calculate the DC current through M1. Then, compare the calculated current to the simulated current. 1.2. Calculate the lambda (a) parameters from the DC current through M1. Does it match the expected channel length modulation effect? 1.3. How large the output swing can be with given DC operating point? 1.4. Please calculate the trans-conductance (9m) of the common-source amplifier. Estimate the transfer function (draw the bode plot) based on the calculated trans-conductance and the schematic given above.
2. AC analysis Run the AC analysis from 1kHz to 1GHz with >20 number of points per decade. 2.1. Simulate the gain of the amplifier and look at the frequency response. Does it match the calculated value from the hand calculation? 2.2. What can you do to increase the pain of the amplifier? Please try to increase the gain by +2dB. 2.3. Design the common source amplifier with PMOS load such that you achieve the small signal gain larger than 3dB. Then, simulate the circuit and find the DC gain and 3dB BW of the circuit. 3. Transient analysis Simulate the circuit with input sinusoidal signal at low frequency, -3dB frequency point, 10x the -3dB frequency point. Please observe the output signal and compare it to the input signal. How large is the signal swing for each case? How much time lag do you observe? Task 2: Design the single-stage common source amplifier with PMOS load and >20dB gain. Please provide the design procedure of your design and the simulation results in LTSpice.