1.3 Use of Flip Flops as "sample and hold" tools Sys AO From Sys To SB Sys B in System A Sample and Hold System B Figure

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1.3 Use of Flip Flops as "sample and hold" tools Sys AO From Sys To SB Sys B in System A Sample and Hold System B Figure 13: Sample and Hold system (interface between Sys A and Sys B). In Figure 13, System A needs to be cascaded with System B: Output of System A is used as input to System 8. System A produces an output value every period T (see Figure 14, left and bottom). However, in each period T system A output transitions before reaching the correct value, which is maintained only for a certain time, before a second transition occurs. As a result, System A real output is affected by transition ripples (see Figure 14, left and top) that should not be fed as input to System B. Specifically: In each period T, system A output undergoes a first transition (transition window 1: tri in Figure 14) before the correct value is reached and maintained (sampling window: sw in Figure 14) till a new transition occurs (transition window 2: tr2 in Figure 14). Implementation detailed are provided in Table 1 (depending on your student ID). Out with transition ripples Out with transition ripples 0.5 WL 0.5 0 0 0 O in 5 1 6 8 5 3 w 4 5 w tri X2 tr8 10- X10 Ideal Out Ideal Out 0.5 0.5) 0 0 3 4 5 6 0 0 8 8 (109 X 109 System A output: ideal (bottom) and real (top) Transition windows (tr1, tr2) and sampling window (sw) Figure 14: System A output example (numerical values may depend on your student ID). Table 1: Implementation and testing details. You may delete from the table the rows that are not relevant to your student 10 Student ID 8" digit is one of: 0,2,4 Duration of transition & sampling windows T-2 mai 1 mss. Om t12 0.5 ms File to use to test "Sample and Hold" EE2504 ACT2_TEST_SnH even low Synchronization signals: already in your test file De you can use those signals in your implementation, No other signal generator allowed. 1 ms 0.1 ms 2 m Sample And Hold Output Sys A Out SampleAndhold Input SampleAndhold Input System Av_even Sync 2 Sync Signal 2 Bin Scope 4 var Sync Sync Signal Only Allowed Signal Generators Even-Low Inot to be modified) 1 Sync 2 O to 1 T=1ms 2 Sync 1 0 to 1 T= 2 ms ie CLK Sice 10) D Flip-Flop
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