SUB \$s2, \$s0, \$s1 # Register $ s 2 written by SUB ADD$4,$s2,$s3 # Register $s2 depend on SUB Assume that each instruc

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Sub S2 S0 S1 Register S 2 Written By Sub Add 4 S2 S3 Register S2 Depend On Sub Assume That Each Instruc 1 (25.77 KiB) Viewed 16 times

SUB \$s2, \$s0, \$s1 # Register $ s 2 written by SUB ADD$4,$s2,$s3 # Register $s2 depend on SUB Assume that each instruction goes through all five stages of the pipeline (Each stage takes one clock cycle): - Stage 1: Fetch instruction (FI) - Stage 2: Decode instruction (DI) - Stage 3: Fetch operands (FO) - Stage 4: Execute instruction (EI) - Stage 5: Write operand (WO) Show how the instructions would progress though this 5 -stage pipeline.