Q2 (80 points)/ Design a synchronous counter, which counts in the sequence 0–1 2–4–70. The counter counts the clock puls

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Q2 80 Points Design A Synchronous Counter Which Counts In The Sequence 0 1 2 4 70 The Counter Counts The Clock Puls 1 (30.29 KiB) Viewed 36 times

Q2 (80 points)/ Design a synchronous counter, which counts in the sequence 0–1 2–4–70. The counter counts the clock pulses if its enable input, w, is equal to 1. If w is equal to 0, the counter stops counting. Using D flip-flops in your FSM, answer the following questions: 1- Draw the state diagram. I 2- Write the state table. 3- Using K-map, implement a suitable circuit for the counter. 4. Is your FSM a Moore- or a Mealy-type machine? 5- Write and simulate the Verilog code for the FSM using Vivado. Show your code, test bench code, and screenshots of your simulation results. Label clearly the inputs and outputs on the screenshots.