ADD, SUB, AND, OR instruction format OP CODE IR[8:6) Rs IR[5:4) Rt IR[3:2) Rd IR(1:0) LI Instruction Format Rd OP CODE I

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Add Sub And Or Instruction Format Op Code Ir 8 6 Rs Ir 5 4 Rt Ir 3 2 Rd Ir 1 0 Li Instruction Format Rd Op Code I 1 (64.26 KiB) Viewed 44 times

ADD, SUB, AND, OR instruction format OP CODE IR[8:6) Rs IR[5:4) Rt IR[3:2) Rd IR(1:0) LI Instruction Format Rd OP CODE IR[8:6] Immediate Value IR[5:2] IR[1:0) Instruction AND OR ADD SUB LI OPCODE 000 001 010 110 100 Instruction Register is a 9-bit register. The most 3 significant bits [8:6) determine the operation. Bits [5:4), (3:2), and [1:0) correspond to source register (Rs), target Register (Rt), and Destination Register (Rd) values, respectively. Rs, Rt, and Rd registers are 2 bits each with 4 possible values (00,01,10,11). These 2 bits are used to choose from 4 different registers, S0, S1, S2, and 3 respectively, cach capable of holding a 4-bit value. Example: An instruction with value 96000101101 corresponds to the following instruction: AND S1, S2, S3; Bit [8:6) = 000 corresponds to AND instruction, Bits (5:41 10 corresponds to S2 register, Bits (3:2)-11 corresponds to $3 register, and Bits[1:03-01 corresponds to S1 register. So, the instruction means; AND the content of $2 register with $3 register and store/write the result in $1 register. The instruction Register is comprised of 9 D-Flip Flops. All D-FFs get the same clock and the flip flops are negative edge triggered. The clock ensures that every clock cycle (falling edge) a new instruction is passed through the components and executed. That is, every clock cycle a new instruction is executed and the result is obtained To implement the 9-bit Instruction Register: 1. Design one negative edge triggered D-Flip Flop module (use BEHAVIORAL MODELING) 2. Use the D-FF module to construct the 9-bit instruction register. (Hierarchical design).