Consider a CMOS inverter, which the following device parameter nMOS VTO, n = 0.8 V pMOS VTO, = -1.0V р unCox = 50 μA/V²

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Consider a CMOS inverter, which the following device parameter nMOS VTO, n = 0.8 V pMOS VTO, = -1.0V р unCox = 50 μA/V² upCox = 20 μA/V² The power supply voltage is VDD = 5V. Both transistors have a channel length of Ln = Lp = 1 um. The total output load capacitance of this circuit is Cout = 2 pF, which is independent of transistors dimensions. i) ii) 3 Determine the channel width of the nMOS and the pMOS transistors such that the switching threshold voltage is equal to 2.2 V, and the output rise time is Trise = 5 ns Calculate the average propagration delay time tp for the circuit designed in (a) How do the switching threshold Vth and the delay times change if the power supply voltage is dropped from 5 V to 3.3 V. Provide the interpretation of the results.