(a) (i) State TWO (2) techniques that can be used for low-power IC design. ( 2 marks) (ii) Elaborate on the effect of ga

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A I State Two 2 Techniques That Can Be Used For Low Power Ic Design 2 Marks Ii Elaborate On The Effect Of Ga 1 (34.25 KiB) Viewed 28 times

(a) (i) State TWO (2) techniques that can be used for low-power IC design. ( 2 marks) (ii) Elaborate on the effect of gate oxide thickness (tox) to the delay and leakage current of transistor in integrated circuit. (4 marks) (b) A CMOS circuit is shown in Figure Q3(b). The circuit should have an equivalent driving capability of an inverter. The minimum length for each transistor in the circuit is 2λ and the electron mobility is three (3) times faster than the mobility of hole. (i) Determine the size of each transistor in the circuit to fulfil the stated requirement. (10 marks) (ii) Calculate the parasitic delay for the circuit and justify whether the calculated parasitic delay is the minimum value. (4 marks)