- Do This Using Verilog 1 (78.34 KiB) Viewed 50 times
Do this using verilog
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answerhappygod
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Do this using verilog
Do this using verilog
$1 SO u V W X 0 0 1 0 1 Figure 3: Implementation idea for 4:1 multiplexer. u u v u V u V 8 Testing multiplexer designs In this lab, we developed a workflow for testing a design that we specified. In this final part of the lab, we will practice using this workflow, so it becomes very comfortable to us. Consider the design in Fig. 3 for a 4:1 multiplexer. This design hierarchically utilizes a 2:1 multiplexer to generate the target output. The target output is given by the following table. V W X sl s2 0 0 W X W X 1 0 V W X 0 1 W uy W X 1 1 X Z Z u Test this design. Use the same testing method that you used in Part 5 to test the Mealy machine. 1. Implement a module mux21 which performs the following simple assignment: assign z = (sel)? a: b; This assignment utilizes the ternary selector operator (...)?...... that is supported by Verilog. Give this module the port list a, b, sel, z. 2. Use the mux21 module to implement the design in Fig. 3 in Verilog. Give this module the name mux41. Give this module the port list u, v, w, x, s1, s2, z and make it the top-level for your lab6 project. 3. Finally, use the testing methodology that you developed in order to test the design.
$1 SO u V W X 0 0 1 0 1 Figure 3: Implementation idea for 4:1 multiplexer. u u v u V u V 8 Testing multiplexer designs In this lab, we developed a workflow for testing a design that we specified. In this final part of the lab, we will practice using this workflow, so it becomes very comfortable to us. Consider the design in Fig. 3 for a 4:1 multiplexer. This design hierarchically utilizes a 2:1 multiplexer to generate the target output. The target output is given by the following table. V W X sl s2 0 0 W X W X 1 0 V W X 0 1 W uy W X 1 1 X Z Z u Test this design. Use the same testing method that you used in Part 5 to test the Mealy machine. 1. Implement a module mux21 which performs the following simple assignment: assign z = (sel)? a: b; This assignment utilizes the ternary selector operator (...)?...... that is supported by Verilog. Give this module the port list a, b, sel, z. 2. Use the mux21 module to implement the design in Fig. 3 in Verilog. Give this module the name mux41. Give this module the port list u, v, w, x, s1, s2, z and make it the top-level for your lab6 project. 3. Finally, use the testing methodology that you developed in order to test the design.