B The Two Edge Triggered Sr Flip Flops Are Shown As In Figure Q3 B I If The Input Are As Shown In Figure Q3 B Ii 1 (81.84 KiB) Viewed 63 times
B The Two Edge Triggered Sr Flip Flops Are Shown As In Figure Q3 B I If The Input Are As Shown In Figure Q3 B Ii 2 (57.43 KiB) Viewed 63 times
(b) The two edge-triggered SR flip-flops are shown as in Figure Q3(b)(i). If the input are as shown in Figure Q3(b)(ii), draw the Q output of flip-flop relative to the clock. Use Appendix 1: Waveform Graph to draw the output waveform. Explain the difference between both flip-flops. (c) S R Q (a) Q(b). CLK Q ## ē R $ R (a) Figure Q3(b)(i) Figure Q3(b)(ii) с (b) ē State TWO(2) applications of sequential logic circuit and its example. [8 marks] [4 marks]
(d) Counter is a specialized register which prescribed sequence of states upon the application of input pulses. (i) (ii) Illustrate a 3-bit Asynchronous Up-counter with the following repeated decimal sequence: 0, 1, 2, 3, 4, 5, 6, 7. Use negative-edge Triggered JK flip-flops. [5 marks] QA QB Qc Figure Q3(d) shows a timing diagram of a 3-bit Asynchronous Up-counter. Illustrate the output waveforms QA, QB and Qc. Use Appendix 2: Waveform Graph to draw the output waveform. л CLK Figure Q3(d) [4 marks]
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