Consider a 6 stage pipeline processor. The number of cycles needed in stages FI - fetch instruction, DI - Decode Instruc

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Consider A 6 Stage Pipeline Processor The Number Of Cycles Needed In Stages Fi Fetch Instruction Di Decode Instruc 1 (45.04 KiB) Viewed 64 times

Consider a 6 stage pipeline processor. The number of cycles needed in stages FI - fetch instruction, DI - Decode Instruction, COA - Calculate Operand Addr, FO - Fetch Operand, El - Execute Instruction, WB - Write Back is shown below for the three instructions 11, 12, and 13: 20 Addr, Fo ΕΙ I-1 1-2 1-3 FI 3 1 2 DI 2 1 2 COA 1 1 1 FO 3 2 2 3 WB 3 2 2 3 2 a. Draw the Time Space diagram for this pipeline with Time (Tx) on the X-axis and Instructions (ly) on Y axis or vice versa. (3) b. If non-pipelined, how many time cycles would be needed to execute the instructions? (1) (1) c. Calculate the speed-up factor for the system