Register $f6 contains the IEEE 754 single precision floating point representation of the negative decimal value -181.25x

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Register $f6 contains the IEEE 754 single precision floatingpoint representation of the negative decimal value -181.25x10-2 and$f7 contains the IEEE 754 single precision floating pointrepresentation of the positive decimal value 2.5 . Show theresulting 32-bit pattern produced in registers $f6 and $f7 if theinstruction add.d $f6,$f6,$f6 is mistakenly executed instead ofadd.s.For a 64-bit "double" operation the MIPS FPU will combine theeven register specified with the next odd register to make a 64-bitregister. This instruction can be considered as add.d$f6 | $ f7, $f6 | $f7, $f6 | $f7, i.e. "Take the 64-bit quantity inthe combined register $f6|$f7, add it to itself, and store it backto the combined register $f6|$f7."Express each answer as an 8-digithex number. a) $f6 contains __________________ b) $f7 contains__________________