10. (10) Assume that the hi and lo registers, used by the mult and div instructions, are read in pipeline stage 2 and ar

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10 10 Assume That The Hi And Lo Registers Used By The Mult And Div Instructions Are Read In Pipeline Stage 2 And Ar 1 (82.96 KiB) Viewed 39 times

10. (10) Assume that the hi and lo registers, used by the mult and div instructions, are read in pipeline stage 2 and are written in pipeline stage 5, like the other CPU registers. Complete the table below to show how the following instructions flow through our MIPS 5-stage pipeline with a data hazard unit but without a data forwarding unit. Insert pipeline bubbles only if and where they are needed. The instructions should be executed in the same order as they appear in the sequence. Include as many additional rows in the table as you need. sll ori sll mult addu mflo ori div mflo $0, $0, 4 $4, $0, -15 $5, $4, 2 $4, $5 $4, $4, $5 $6 $3, $0, 16 $6, $3 $7 Clock cycle Fetch 1 2 3 Decode Execute Memory Write-back