8.10 Draw the timing diagram for V and Z for the circuit. Assume that the AND gate has a delay of 10 ns and the OR gate
Posted: Sun Jul 03, 2022 12:14 pm
8.10 Draw the timing diagram for V and Z for the circuit. Assume that the AND gate has a delay of 10 ns and the OR gate has a delay of 5 ns. W X Y V Z 0 10 ns 5 ns Z 5 10 15 20 25 30 35 40 45 50 55 t (ns)