You have a modulo-256 down counter (operand counter) with 8-bit output and one-bit input N (the operand counter counts d

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You Have A Modulo 256 Down Counter Operand Counter With 8 Bit Output And One Bit Input N The Operand Counter Counts D 1 (47.35 KiB) Viewed 18 times

a) Design a circuit that outputs Z=1 if the operand counter is nonzero. b) The following FSM state diagram receives input Z and outputs N (which decrements the down counter) and R (which increments the up counter). When the down counter reaches zero, algebraically describe the value of the up-counter W in terms of the initial value of the down counter V. Also, denote if the answer will be rounded down or rounded up to the nearest integer. Z/NR 1/11 RESET 1/10 0/00 1/00 0/00 0/00 0/00 1/06 1/11 0/00 0/00 8 1/11 c) Design a FSM state diagram that fills the result counter with the value W = (the result of division rounded down to the nearest integer) using the one-bit input Z, output R (R is the input which enables the up counter), and output N (N is the input which enables the down counter). You only need to draw the state diagram; the destination for each FSM connection should be specified as above. When the result counter contains the correct value, the result counter should remain unchanged for any future clock cycles. d) Repeat part II but produce the result W = = (here, the quotient is rounded up to the nearest integer). e) Repeat part II but produce the result W = [] (round up).