improved performance! 4.10 When processor designers consider a possible improvement to the processor datapath, the decis

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Improved Performance 4 10 When Processor Designers Consider A Possible Improvement To The Processor Datapath The Decis 1 (67.83 KiB) Viewed 11 times

improved performance! 4.10 When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise 4.7, and the following costs: 1-Mem 1000 Register File 200 Mux ALU Adder D-Mem 10 100 30 2000 Single Register 5 Sign extend 100 Single gate 1 Control 500 Suppose doubling the number of general purpose registers from 32 to 64 would reduce the number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps to 160 ps and double the cost from 200 to 400. (Use the instruction mix from Exercise 4.8 and ignore the other effects on the ISA discussed in Exercise 2.18.) 4.10.1 [5] <$4.4> What is the speedup achieved by adding this improvement? 4.10.2 [10] <$4.4> Compare the change in performance to the change in cost. 4.10.3 [10] <$4.4> Given the cost/performance ratios you just calculated, describe a situation where it makes sense to add more registers and describe a situation where it doesn't make sense to add more registers.