ARM Accredited Engineer Questions + Answers

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Question 1
Which of these C99 keywords can be used to indicate that two arrays do not overlap?
A. "pure"
B. "volatile"
C. "static"
D. "restrict"


Answer : D

Question 2
How many bytes of stack are needed to pass parameters when calling the following function? int foo( short arg_a, long long arg_b, char arg_c, int arg_d )
A. 0
B. 4
C. 8
D. 15


Answer : C

Question 3
In the Generic Interrupt Controller (GIC), when an interrupt is requested, but is not yet being handled, it is in which of the following states?
A. Inactive
B. Active
C. Pending
D. Edge-triggered


Answer : C

Question 4
In an ARMv7 processor that includes the Advanced SIMD (NEON) extension, how many single precision floating point values can be stored in the Q0 register?
A. 1
B. 2
C. 4
D. 8


Answer : C

Question 5
Printf statements could be used to achieve which of the following debug tasks?
A. Observe changes to a local variable in a function
B. Capture a real-time trace of program execution
C. Debug boot code, before a call to the C main() function
D. Stop the processor at an interesting location in the code


Answer : A


Question 6
An Advanced SIMD intrinsic has the prototype:
int16x4_t vmul_n_s16(int16x4_t a, int16_t b);
How many multiplications does this intrinsic compute?
A. 1 multiplication
B. 4 multiplications
C. 16 multiplications
D. 64 multiplications


Answer : B

Question 7
Cross compiling enables a programmer to:
A. Produce a binary object that will run on processors based on any architecture.
B. Mix different source languages within the same source file and compile with a single tool.
C. Run code written for one processor on a processor based on a different architecture.
D. Compile target code using a computer based on a different architecture.


Answer : D

Question 8
Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)
A. Thumb is a hybrid 16/32-bit instruction set
B. No Thumb instructions can be conditionally executed
C. Thumb code is always slower than the equivalent ARM code
D. Some routines take more instructions in Thumb code than in the equivalent ARM code
E. The Thumb instruction set can access the Advanced SIMD "NEON" instructions
F. Thumb code is always more power-efficient than equivalent ARM code


Answer : A,D,E

Question 9
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
A. FIQ exceptions must not be taken
B. The instruction cache must be enabled
C. Global variables must be initialized to zero
D. The Reset Vector must reside in non-volatile memory


Answer : D

Question 10
Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?
A. No, they are completely incompatible
B. Yes, all Cortex-A9 MPCore processors include an integrated GIC
C. Yes, but a dummy second processor has to be included
D. No, a GIC is only compatible with multi-core Cortex-A9 processors


Answer : B


Question 11
What architecture does the ARM11 MPCore implement?
A. ARMv6
B. ARMv6K
C. ARMv7-A
D. ARMv7-A with the Multiprocessing Extensions


Answer : B

Question 12
Under which of the following circumstances would a DSB instruction be used?
A. In a multi-threaded system, when two threads need to be synchronized at a particular point
B. When accessing a peripheral, it is necessary to halt until the memory access is complete
C. When it is necessary to temporarily disable interrupts while carrying out a particular memory access
D. In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task


Answer : B

Question 13
The Cortex-A9 processor implements a feature called "small loop mode" which reduces power consumption when executing small loops by turning off instruction cache accesses.
Which of the following statements describes a condition that must be satisfied for this mode to be enabled?
A. The loop must fit into two cache lines
B. The loop must only contain forward branches
C. Only integer arithmetic can be used
D. All variables must be held in registers


Answer : A

Question 14
The following function is declared: float func(float fl, float f2);
The file file1 .c contains a call to func, and is compiled with hard floating point linkage. The file file2.c contains the definition of func, and is compiled with AACPS soft floating point linkage.
Assume that the two files are successfully linked using the ARM linker and an executable is generated. The generated executable:
A. Exhibits correct behavior, but suffers a performance penalty because the linker has to generate extra code.
B. Exhibits correct behavior, and suffers no performance penalty.
C. Will not execute.
D. Exhibits incorrect behavior.


Answer : D

Question 15
What is the maximum value of the immediate field in an ARM SVC instruction?
A. 0x0
B. 0xF
C. 0xFF
D. 0xFFFFFF


Answer : D


Question 16
In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!
A. 0x80003FF8
B. 0x80004000
C. 0x80004008
D. R1 contents are unpredictable


Answer : B

Question 17
Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:
A. A simpler branch instruction can be used.
B. Decrementing variables uses less power than incrementing them.
C. The decrement and branch operations can be encoded as a single instruction.
D. The loop termination condition check can be integrated into the subtract operation.


Answer : D

Question 18
A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes.
How many bits are required to index a cache line in a way?
A. 6 bits
B. 7 bits
C. 9 bits
D. 15 bits


Answer : B

Question 19
The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread: data = 123; ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
A. DSBSY
B. DSBST
C. DMBSY
D. DMBST


Answer : D

Question 20
Which of the following ARM processors has a superscalar micro architecture?
A. ARM926EJ-S
B. Cortex-M0
C. Cortex-M3
D. Cortex-A8


Answer : D



Question 21
Which of the following instructions can be used to enter a power saving mode?
A. PLD
B. PLI
C. WFE
D. DSB


Answer : C

Question 22
A standard performance benchmark is being run on a single core ARM v7-A processor.
The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?
A. L1 Caches and branch prediction are disabled
B. The Embedded Trace Macrocell (ETM) is disabled
C. The Memory Management Unit (MMU) is enabled
D. The Snoop Control Unit (SCU) is disabled


Answer : A

Question 23
Which of the following statements is TRUE with respect to the power consumption related to memory accesses?
A. Accessing a large memory device consumes less power than accessing a small one
B. A series of non-sequential accesses is more efficient than a series of sequential accesses
C. Increasing the size of the cache will always reduce power consumption for a given application
D. Storing frequently used data in Tightly Coupled Memory will reduce power consumption


Answer : D

Question 24
The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?
A. Hard floating-point linkage
B. Soft floating-point linkage without floating-point hardware
C. Hard floating-point linkage with optimization for space
D. Soft floating-point linkage with floating-point hardware


Answer : B

Question 25
When using the default ARM tool-chain libraries for bare-metal applications. I/O functionality is rerouted and handled by a connected debugger. This is often referred to as semihosting. Which one of the following explanations BEST describes how this feature can be implemented by a debugger?
A. The library directly sends I/O requests to the debugger using the JTAG connection
B. While the target is running, the debugger processes I/O requests from a shared queue in memory
C. The I/O library calls rely on an Ethernet connection to redirect the requests to the debugger
D. The I/O library calls generate an exception that is trapped and handled by the debugger


Answer : D


Question 26
The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?
A. Cache Size
B. Clock Speed
C. Program size
D. Numbers of instructions executed


Answer : D

Question 27
The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?
A. Translates virtual addresses to physical addresses
B. Generates parity information to detect soft errors in memory
C. Performs access permission checks
D. Permits the system to be divided into secure and normal worlds, through the use of ARM's TrustZone technology


Answer : C

Question 28
In which of these cases would code have better performance when compiled for Thumb state than when compiled for ARM state?
A. When the processor has no data cache
B. When the code involves many shifting operations
C. When the code has many conditionally executed instructions
D. When the processor can only fetch instructions 16-bits at a time


Answer : D

Question 29
According to the AAPCS (with soft floating point linkage), when the caller "func" calls sprintf, where is the value of the parameter "x" placed?
#include <stdio.h>
void func(double x, int i , char *buffer)
sprintf(buffer, "pass %d: value = %f\n", i, x); }
A. Split between register R3 and 4 bytes on the stack
B. Split between registers R3 and R4
C. 8 bytes on the stack
D. VFP Register D0


Answer : C

Question 30
Which of the following statements best describes a Board Support Package (BSP)?
A. PC interface hardware for configuring a boot monitor
B. Hardware specific source code needed for operating system support
C. A working port of Linux for a specific hardware platform
D. Debugging hardware and software supplied with a development board


Answer : B


Question 31
A simple system comprises of the following memory map:

Flash - 0x0 to 0x7FFF -

RAM - 0x10000 to 0X17FFF -
When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?
A. Top address of RAM (0x18000)
B. Top address of flash (0x8000)
C. Bottom address of RAM (0x10000)
D. Bottom address of flash (0x0000)


Answer : A

Question 32
Assume a Big-Endian (BE) memory system with the following memory contents.

Byte Address Contents -
0x100 0x11
0x101 0x22
0x102 0x33
0x103 0x44
If R5 = 0x100, what are the contents of R4 after performing the following operation?
LDR R4, [R5]
A. 0x11223344
B. 0x44332211
C. 0x22114433
D. 0x33441122


Answer : A

Question 33
An Advanced SIMD intrinsic has the prototype:
uint8xl6x2_t vld2q_u8 (uint8_t const * ptr);
How many bytes does this intrinsic load from memory?
A. 2
B. 16
C. 32
D. 256


Answer : C

Question 34
When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)
A. Coherency management between all L1 data caches
B. Broadcast of some inner-shared cache and TLB maintenance operations
C. Broadcast of some outer-shared cache and TLB maintenance operations
D. Coherency management between all L1 instruction caches
E. Coherency management between all external caches


Answer : A,B

Question 35
In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a
Non-secure privileged mode?
A. The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory
B. Secure memory contents are encrypted, and cannot be decrypted by Non-secure software
C. The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set
D. The MMU generates an abort on accesses to Secure memory performed by Non-secure software


Answer : A


Question 36
Which TWO of the following interrupt types does a Generic Interrupt Controller (GIC) support? (Choose two)
A. Interrupt from a private peripheral to a processor
B. Interrupt from a processor to a private peripheral
C. Interrupt from a shared peripheral to a processor
D. Interrupt from a processor to a shared peripheral
E. Interrupt from a private peripheral to a shared peripheral
F. Interrupt from a shared peripheral to a private peripheral


Answer : A,C

Question 37
The effect of clicking the Stop button in a debugger is to:
A. Put the processor(s) into debug state.
B. Force the processor to execute a BKPT instruction
C. Hold the processor in a Reset condition
D. Re-initialize the memory contents.


Answer : A

Question 38
When using an Operating System, which of the following operations can NOT typically be done by user processes?
A. Reading the link register (R14)
B. Reading data from the user stack
C. Changing from ARM state to Thumb state
D. Changing the interrupt mask bits (A, I, F) in the CPSR


Answer : D

Question 39
Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)
A. Unaligned accesses may take more cycles to execute than aligned accesses
B. Unaligned loads and stores are necessary for accessing fields in packed structures
C. A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices
D. If the relevant control register setting is enabled all loads and stores can function from unaligned addresses
E. Unaligned accesses can only be made to Normal memory


Answer : A,E

Question 40
When should an ISB instruction be used?
A. When executing a long branch
B. When clearing the branch predictor caches
C. When reading a register from a coprocessor
D. When returning from an exception handler


Answer : B


Question 41
In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)
A. The time spent waiting for I/O operations
B. The time taken to download the program via the debugger
C. The time taken for memory accesses
D. The time taken for the CPU to execute instructions
E. The time taken to compile the source code
F. The time taken to perform instruction tracing


Answer : A,C,D

Question 42
In general, when programming in C, stack accesses will be reduced by:
A. Disabling inlining.
B. Never passing more than four parameters in function calls.
C. Declaring automatic variables as "packed".
D. Configuring the compiler to optimize for space.


Answer : B

Question 43
Which of these instructions is a correct translation of the body of function f? struct T { char a; int b; }; int f(struct T *p) { return p->b; }
A. LDR r0, [r0], #1
B. LDR r0, [r0]. #4
C. LDR r0, [r0.#1]
D. LDR r0, [r0. #4]


Answer : D

Question 44
When using a Generic Interrupt Controller (GIC), how does code cause a software- generated interrupt?
A. By executing an SGI instruction
B. By writing to a register in the GIC
C. By writing to the F bit in the CPSR
D. By writing to the I bit in the CPSR


Answer : B

Question 45
The ARMv7-A virtual memory management system supports 32-bit (short) and 64-bit (long) page table descriptors. The sizes of a small page in a short descriptor and a small page in a long descriptor are:
A. 1 KB and 4KB respectively
B. 4KB and 4KB respectively
C. 4KB and 16KB respectively
D. 16KB and 16KB respectively


Answer : B