Given logical identification of memory bits and timing devices in the images below, what is the state of outputs Q1 and

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Given Logical Identification Of Memory Bits And Timing Devices In The Images Below What Is The State Of Outputs Q1 And 1 (197.8 KiB) Viewed 29 times

Given logical identification of memory bits and timing devices in the images below, what is the state of outputs Q1 and Q2 after the rung conditions in the ladder segment become true? St2_00 HE M02 T5 elapsed St5_10 Q1=1, Q2=0 Enable T5 Q1=0, Q2=0 O Q1=0, Q2=1 O Q1=1, Q2=0 O Q1=1, Q2=1 TO2 RESET St1_Init Q1=0, Q2=0 T4 elapsed St4_11 Q1=1, Q2=1 Enable T4 ENABLE T3 elapsed St3_01 M03 St2_00 St3_01 St2_00 M02 Q1=0, Q2=0 Enable T2 T2 elapsed Q1=0, Q2=1 Enable T3