- R S T D S T K G Oh S H S G S C S Q2 Consider The System Given Above With G S 0 6 E Tas H S 1 Where The Time 1 (10.11 KiB) Viewed 34 times
Q2) Consider the system given above with G(s) 0.6 e-Tas ,H(s) = 1 where the time-delay 0.3 s + 1 is Ta = 20 ms and the sampling period is T = 20 ms. Then, answer the following questions. = a) Draw the root locus plot for D(s) = K. b) Design a digital controller which makes the closed loop system steady state error zero to step inputs and the closed-loop system poles double on the real axis. c) Find the settling time and the overshoot of the digital control system with the controller you designed in (b). d) Simulate the response of the with your designed controller for unit step input in Simulink by constructing the block diagram. Provide its screenshot and the system response plot. Note: Q2 should be solved by hand instead of (d). You can verify your results by rlocus and sisotool commands in MATLAB.