Task 2: Discrete Op-Amp/Multi-Stage Amplifier Design [Max. 60 Marks] In this task you are going to design a multi-stage

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Task 2 Discrete Op Amp Multi Stage Amplifier Design Max 60 Marks In This Task You Are Going To Design A Multi Stage 1 (108.4 KiB) Viewed 22 times

Task 2: Discrete Op-Amp/Multi-Stage Amplifier Design [Max. 60 Marks] In this task you are going to design a multi-stage Amplifier using 2N3904 (NPN) and 2N3906 (PNP) transistors. The basic architecture for an Op-Amp will contain a differential input stage, followed by a CE Amplifier and an output stage as shown in Figure 2. Vin+ Vin- Differential Pair CE Amplifier The basic specifications for the multistage are outlined below: Figure 2: Multi-Stage Amplifier Block Diagram • Open loop-gain (A): > 80 dB (10000 V/V) input impedance (Rin) > 100 ks • output impedance (R₂) < 75 • CMRR > 100dB. • Vcc= -VEE = 15V • Phase Margin > 70⁰ • Slew Rate • Offset Voltage Output Stage