Assume the following: The memory is byte addressable. Memory accesses are to 1-byte words (not to 4-byte words). Address

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Assume the following:
The memory is byte addressable.
Memory accesses are to 1-byte words (not to 4-byte words).
Addresses are 13 bits wide.
The cache is two-way set associative (E = 2), with a 4-byte block size (B = 4) and eight sets (S = 8).
The contents of the cache are as follows, with all numbers given in hexadecimal notation.
The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
For this cache, list all of the hexadecimal memory addresses that will hit in set 3.
Check all that apply.