This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address L

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answerhappygod
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This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address L

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This exercise is about address translation on an x86 Intel CPU.This CPU translates (using hardware) a logicaladdress LA into a physicaladdress PA as follows:
This Exercise Is About Address Translation On An X86 Intel Cpu This Cpu Translates Using Hardware A Logical Address L 1
This Exercise Is About Address Translation On An X86 Intel Cpu This Cpu Translates Using Hardware A Logical Address L 1 (169.36 KiB) Viewed 29 times
Please explain how those answers were derived. Pleasedon't copy someone else's answers answers so that someoneelse who knows how to solve this can help me. Thank you.
Fill in multiple blanks. (Your answer must be given in hexadecima: do not forget "h" at the end) This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA 10h*CS + IP Suppose DS = Ox2000 and CS = 0x0000. This question is about the instruction I that accesses data in memory. Let this memory access instruction I be at address 7000h MOV SI, 3000h MOV BX, [SI] The physical address of the memory access instruction is 07000h 23000h and the physical address of its memory operand is
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