- Page 2 Of 3 Eel 6506 N Ghani Spring 2021 Test 1 Name 5 Scheduler Design Consider The Following Input Packet Sequen 1 (47.83 KiB) Viewed 61 times
Page 2 of 3 EEL 6506 (N. Ghani, Spring 2021) Test 1 Name: 5) Scheduler Design Consider the following input packet sequen
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Page 2 of 3 EEL 6506 (N. Ghani, Spring 2021) Test 1 Name: 5) Scheduler Design Consider the following input packet sequen
Page 2 of 3 EEL 6506 (N. Ghani, Spring 2021) Test 1 Name: 5) Scheduler Design Consider the following input packet sequence/timing at an output-buffered switch link (all packets arrive fully at the beginning of their respective timeslots): Arthal Times Packet Transmission Times 6,-0.2 (GPS. VC) slot (WRR) Pa Buffer 1 Isot Po PP 02-0.4(GPS, VC) 3 slot (WRR) Buffer 2 6, 0:3 (GPS, VO 2 slots (WRR) P Buffer 0.1(GPS, VC) Isot (WRR) Pa Buffer 4 A. What is the first packet that completes transmission in the idealized generalized processor sharing (GPS) scheduler? At what time is it sent? B. What is the output sequence/timing for packets with priority scheduling (priority 1-2-3-4) C. List the output packet sequence/timing for all packets for a non-work-conserving weighted round robin (WRR) scheduler with a frame-size of 7 slots (allocations shown). What is the total transmission time? D. Repeat for a virtual clock scheduler. What is the total transmission time?
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