DE1-SOC

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DE1-SOC

De1 Soc 1 (59.01 KiB) Viewed 73 times

De1 Soc 2 (29.13 KiB) Viewed 73 times

De1 Soc 3 (54.49 KiB) Viewed 73 times

Part V Consider the circuit shown in Figure 7. It uses a two-bit Wide 4-to-1 multiplexer to enable the selection of four characters that are displayed on a 7-segment display. Using the 7-segment decoder from Part IV this circuit can display the characters d. E. 0. 1. 2. or blank" depending on your DE-series board. The character codes are set according to Table 2 by using the switches SW-6, and a specific character is selected for display by setting the switches SW-5. An outline of the VHDL code that represents this circuit is provided in Figure 8. Note that we have used the circuits from Parts III and IV as subcircuits in this code. You are to extend the code in Figure 8 so that it uses four 7-segment displays rather than just one. You will need to use four instances of each of the subcircuits. The purpose of your circuit is to display any word on the three 7-segment displays that is composed of the characters in Table 2, and be able to rotate this word in a circular fashion across the displays when the switches SW- are toggled. As an example, if the displayed word is dE10, then your circuit should produce the output patterns illustrated in Table 3. sw, SW 0 SW SW 00 10 11 7-segment decoder SW Figure 7: A circuit that can select and display one of four characters SW. 01 Characters 00 DE O EI Od 10 10 de 11 0 0 E1 Table 3: Rotating the word dE10 on four displays. Perform the following steps 1. Create a new Quartus project for your circuit. 2. Include your VHDL entity in the Quartus project. Connect the switches SW-s to the select inputs of each of the three instances of the two-bit wide 3-to-1 multiplexers. Also connect SW-e to each instance of the multiplexers as required to produce the patterns of characters shown in Table 2. Connect the SW switches to the red lights LEDR, and connect the outputs of the three multiplexers to the 7-segment displays HEX2. HEX) and HEXO. 3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment dis- plays. Compile the project. 4. Download the compiled circuit into the FPGA chip, Test the functionality of the circuit by setting the proper character codes on the switches SW3-0 and then toggling SW s to observe the rotation of the characters.
LIBRARY USE iece. And_logic_1164all: ENTITY part is PORT (SW IN STD LOGIC VECTOREO DOWNTO OY LETROUT SID LOGIC VECTORIO DOWNTOOR HEXO: OUT STD LOGIC VECTORIO TO 6X END ARCHITECTURE Behavior of parts IS COMPONENT murat_2001 PORT (S. U, V, W.X IN STD_LOGIC_VECTORI DOWNTOOK M OUT STD LOGIC VECTORI DOWNTO OX END COMPONENT: COMPONENT char_7weg PORTC IN STD LOGIC VECTORI DOWNTOOL Display OUT STD LOGIC_VECTORIO TO END COMPONENT SIGNAL. MO: STD LOGIC_VECTORI DOWNTOOK BEGIN Umuhi_4601 PORT MAP (SW) DOWNTOR). SWOT DOWNTO G.SWS DOWNTO4. SWO DOWNTO 2). SWI DOWNTO O MOK O char_7 PORT MAP (MO, REXOX END Behavior LIBRARY USE sedlogic. 1164 - implements a 2-bit Wide 4 col multiplexer ENTITY must 43 PORT (SU, V W X IN STD LOGIC VECTOR I DOWNTOOK OUT STD LOGIC VECTORI DOWNTOOR END MIN 4001 ARCHITECTURE OF Zhl_tol IS code show END Behavior LIBRARY USE etdJopic_1164all ENTITY cha Twey Is PORTC IN STD LOGIC_VECTORI DOWNTOOK Dupla OUT STD LOGIC VECTORIO TO 6 END due ARCHITECTURE Behavior of char. They Is cade show END Behavice Figure VHDN code fix the circuit in Figure?
Part VI Extend your design from Part V so that is uses all 7-segment displays on your DE-series board. Your circuit needs to display a three or four-letter word, corresponding to Table 2, using "blank" characters for unused displays Implement rotation of this word from right-to-left as indicated in Table 4 and Table 5. To do this, you will need to connect 6-to-1 multiplexers to each of six 7-segment display decoders for the DEIO-Lite, DED-CV and DEI SOC. Note that for the DEIO-Lite you will need to use 3-bit codes for your characters, because five characters are needed when including the "blank" character (your 7-segment decoder will have to use 3-bit codes, and you will need to use 3-bit wide 6-to-1 multiplexers). For the DE2-115, you will need to connect 8-to-1 multiplexers to cach of the eight 7-segment display decoders. You will need to use three select lines for each of the multiplexers connect the select lines to switches SW-7. In your VHDL code connect constants to the 6-10-1 for 8-to-1) multiplexers that select each character, because there are not enough SW switches SW-1 Character pattern 000 EIO 001 MEIO 010 d E10 011 E10 100 10 d E 101 0 dE1 Table 4. Rotating the word dE10 on six displays. d SW,-- 000 001 010 011 100 101 110 111 Character pattern de 2 dE2 dE2 d E 2 dE2 E 2 2 d d E d E 2 Table 5: Rotating the word dE2 on eight displays. Perform the following steps: 1. Create a new Quartus project for your circuit. 2. Include your VHDL entity in the Quartus project. Connect the switches SW-7 to the select inputs of each instance of the multiplexers in your circuit. Connect constants in your VHDL code to the multiplexers as required to produce the patterns of characters shown in Table 4 or Table 5 depending on your DE-series board. Connect the outputs of your multiplexers to the 7-segment displays HEXS. HEXO of the DEIO- Lite, DEO-CV and DEI-SoC or HEX... HEXO for the DE2-115 3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment dis- plays. Compile the project 4. Download the compiled circuit into the FPGA chip, Test the functionality of the circuit by toggling SW-: to observe the rotation of the characters.