- Complete The Following Without A Load Capacitor 1 Design A Simple 3 Input Nand Gate In Cmos Logic Note You Will Need T 1 (143.81 KiB) Viewed 56 times
perform raise/fall delays analysis using Multisim.
For this exercise you will be using a 45nm bulk CMOS technology
for your simulations. The SPICE parameter values are as follows:
45nm process technology Vdd = 1.0V Low‐Vth‐N = 0.22, Low Vth‐P
= − 0.17 (approx.) High‐Vth‐N = 0.35, High Vth‐P = −0.33
(approx.
Complete the following without a load capacitor 1. Design a simple 3-input NAND gate in CMOS logic. Note you will need to design your NAND gate from scratch, at the transistor level. Use low-Vth (VTL) devices. Assume a minimum sized transistor with W./Ln = Wp/Lp =3, where In = Lp = 50nm (allowing for Left = 45nm) and un/up =2. (Hint: Use Virtual transistors, click on 'Edit model to change Vth (VTO/threshold voltage) 2. Carry out a theoretical analysis on paper first, describe and explain the input patterns that produce the worst-case rise/fall delays. 3. 4. Simulate and demonstrate correct logical and electrical behaviour with input patterns that produce worst-case rise/fall delays from your paper analysis. Report the worst- case rise/fall delays. Describe and explain the input pattern that dissipates the highest dynamic current (i.e. the one that has the highest drain current Id when the output switches). Then use Multisim to obtain the average dynamic power in your circuit. In this case, average current is measured during the rise time and fall time (0.1*Vdd to 0.9*Vdd). Repeat steps 1-4 for a 3-input NAND gate implemented with high-Vth (VTH) 5. daviaan