P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions

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P2 Draw The Schematic Of The Cmos Logic Gate That Implements The Function Y A Bc A Identify The Input Conditions 1 (88.62 KiB) Viewed 65 times

P2) Draw the schematic of the CMOS logic gate that implements the function Y = A + BC. (a) Identify the input conditions for the worst-case rise/fall times and the best case rise/fall times. (b) Size your transistors, such that for the worst case the gate achieves the same rise and fall times of the unit-sized inverter of P1 when your gate is driving a load capacitance of 1.5pF. (c) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the worst case rise and fall time of your gate and compare them to that of the unit-sized inverter in Pl. (d) Using the equivalent resistance to model the transistors and neglecting the diffusion capacitances, estimate the best case rise and fall time of your gate.