. Procedure 1. Construct four circuits (using only AND, OR and INVERTOR logic devices) to verify each DeMorgan Theorem i

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Procedure 1 Construct Four Circuits Using Only And Or And Invertor Logic Devices To Verify Each Demorgan Theorem I 1 (44.87 KiB) Viewed 57 times

Procedure 1 Construct Four Circuits Using Only And Or And Invertor Logic Devices To Verify Each Demorgan Theorem I 2 (21.79 KiB) Viewed 57 times

. Procedure 1. Construct four circuits (using only AND, OR and INVERTOR logic devices) to verify each DeMorgan Theorem in Multisim using the PLD design. All circuits should be in the same file. The first circuit should represent the formula A+B , the second circuit should represent ĀB, the third circuit should represent AB, and the fourth will represent Ā+ B. All circuits should be connected to the same inputs (SW1-A, SWO™B), and each input should have the corresponding numbered LED to represent its value (Ex. SW1 should also be connected to LED1) 2. The output LED connected to each Boolean Expression should be put near the Boolean expressions in Tables 1 and 2. 3. Save the files as "DeMorgan's Theorem_Basys 3". 4. Bring the downloaded circuit to the lab. 5. In the lab section, download the file to Basys 3, and fill out Table 1 and Table 2 6. To complete the experiment, answer questions 1-5. Input Output A (LED1) B (LED) A B (LED15) A. BLED 14) 0 0 0 1 1 0 1 Table 1-Output Verification of DeMorgan's First Theorem Input Output A (LED1) B (LED O) A. B (LED13) AB(LED12) o 0 0 1 1 0 1 1 Table 2-Output Verification of DeMorgan's Second Theorem
a. Questions 1. According to Demorgan's theorems, NAND gate is equivalent to (Bubbled OR / Bubbled AND) NOR gate is equivalent to --(Bubbled OR / Bubbled AND For Questions 2-5, place your answers on separate paper to attach to your lab experiment. 2. Apply De Morgan's theorems for the following expressions: a. (A+B) + C b. (A+B) + CD ABC + ( + E) b. d AB (CD+EF) e AB ( CD) 3. Simplify: (A+B) (C+D) (A+B) (C-5) 4. Draw the circuit diagram for the following equation using ONLY NAND-NAND logic. ĀB+BC +A 5. Using only basic gates draw the logic diagram for: Y = AB + AB