7. Considering a full adder with the symbol and truth table shown below (Fig. 4- 4) (a) (4%) Please implement the full a

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7 Considering A Full Adder With The Symbol And Truth Table Shown Below Fig 4 4 A 4 Please Implement The Full A 1 (546.02 KiB) Viewed 71 times

7. Considering a full adder with the symbol and truth table shown below (Fig. 4- 4) (a) (4%) Please implement the full adder with AND, OR, and inverter gates (b) (4%) Please implement the full adder with a 3-to-8 line decoder (with symbol and truth. table shown below, Fig. 9-17) and some gates (C) (4%) Please implement the full adder with two half-adders (with symbol and truth table. shown below) and some gates. (d) (3%) If the propagation delay of both the AND gate and OR gate is 5ns and the propagation delay of the inverter gate is 2ns, please calculate the propagation delay of the full adder implemented in the three different ways specified in (a), (b), and (c), respectively.