3 HO -D 7240C Consider the circuit in the figure which is loaded by a load capacitor of Cload=240C, while the input capa

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3 Ho D 7240c Consider The Circuit In The Figure Which Is Loaded By A Load Capacitor Of Cload 240c While The Input Capa 1 (64.51 KiB) Viewed 49 times

3 HO -D 7240C Consider the circuit in the figure which is loaded by a load capacitor of Cload=240C, while the input capacitance is in- 8 Cin=8C (as indicated on NAND2). 2x (C is the unit capacitance, i.e. gate or drain/source out capacitance of a minimum-size nMOS transistor) 3y a) By using the effort delay method, calculate the sizes of the gates with unknown sizes, which satisfy the minimum delay from in to out (nMOS and PMOS sizes should also be determined for each gate). Then, calculate the total normalized delay d from in to out. b) Assume that, as a designer you are not satisfied with the delay, so you decide to insert an extra inverter between 240C and NAND3 (sized 3y), hoping to obtain a smaller delay. Apply the optimization again for this case to re-obtain the values of x, y and z (z: size of the extra inverter). Then, re-calculate the total normalized delay d to see whether you managed to reduce it (No need to calculate nMOS/PMOS sizes here).