Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3..QO', are cleared to logic-0 asyn

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Table B2a Shows The Output Sequence Of A Synchronous Counter The Counter Outputs Q3 Qo Are Cleared To Logic 0 Asyn 1 (71.79 KiB) Viewed 44 times

Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3..QO', are cleared to logic-0 asynchronously, by asserting the 'Rst' input. With 'Rst' at logic-0, the counter outputs change on the positive-edge of the 'Cik' input. Upon reaching output state <Q3, Q2, Q1, QO> = <1, 0, 0, 0>, the counter returns to state <0, 0, 0, 1> and repeats the sequence as long as 'Rst' is negated. (a) Design a synchronous counter to implement the behaviour shown in table B2a, making use of the flip-flop shown in figure B2a (assume that clear (CLR) inputs is active-high). Fully record all design steps and draw a labelled logic diagram of your design. (14 marks) D Q Cik ä Rst Figure B2a The counter designed in part (a) is to be described using the Verilog-HDL. Listing B2a below shows an incomplete description of the counter. Making use of module-instantiation statements. //module header for D-type Flip-flop with asynchronous clear module DFFC(input D, CLK, CLR, output 0);