Figure B1a shows a state diagram for a digital circuit that produces a 3-bit pattern. Assume that a synchronous counter

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Figure B1a Shows A State Diagram For A Digital Circuit That Produces A 3 Bit Pattern Assume That A Synchronous Counter 1 (78.94 KiB) Viewed 51 times

Figure B1a shows a state diagram for a digital circuit that produces a 3-bit pattern. Assume that a synchronous counter is to be designed that produces the 3-bit output sequence shown in figure B1a. Reset 0 - 6 1 1 2 N 0 Figure B1a (a) Write down a state table showing the binary output sequence of the circuit, listed in the same order that they occur on the state diagram. (4 marks) (b) Briefly describe any changes to the state diagram that may be necessary, to make the design realisable. Illustrate your proposed changes by drawing a modified version of the state diagram (4 marks) (c) Answer the following questions: i. How many D-type flip-flops would you need to implement the modified diagram? How many possible states are needed to be taken into account? What would be the size of the K-map? (4 marks)