VHDL Modeling and Testbench The circuit below shows a 4 bit adder-subtractor. Create a simulation Testbench to verify yo

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VHDL Modeling and Testbench
The circuit below shows a 4 bit adder-subtractor.

Vhdl Modeling And Testbench The Circuit Below Shows A 4 Bit Adder Subtractor Create A Simulation Testbench To Verify Yo 1 (13.12 KiB) Viewed 106 times

Create a simulation Testbench to
verify your design above. Your testbench should report by
using ASSERT, with a severity
of WARNING should the output be
incorrect. You may choose any 4 sets of 2x4-bit number as
stimulus for your testbench. 2 sets for addition operation and the
other 2 for subtraction.
C4 A3 B3 \1 0, 1-bit Full Adder S3 C3 A2 B2 1 0, 1-bit Full Adder · S2 C2 Α1 Β1 1 0, 1-bit Full Adder S1 C1 Ao Bo 1 0, 1-bit Full Adder So Co D