11:46 1 4G Model Exam 2 (1) Read Only - Save a copy to edit. Save a copy Sof: 12 Q4. (Marks - 9) Given the state-diagram

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11 46 1 4g Model Exam 2 1 Read Only Save A Copy To Edit Save A Copy Sof 12 Q4 Marks 9 Given The State Diagram 1 (33.3 KiB) Viewed 35 times

11 46 1 4g Model Exam 2 1 Read Only Save A Copy To Edit Save A Copy Sof 12 Q4 Marks 9 Given The State Diagram 2 (33.59 KiB) Viewed 35 times

11 46 1 4g Model Exam 2 1 Read Only Save A Copy To Edit Save A Copy Sof 12 Q4 Marks 9 Given The State Diagram 3 (27.11 KiB) Viewed 35 times

11:46 1 4G Model Exam 2 (1) Read Only - Save a copy to edit. Save a copy Sof: 12 Q4. (Marks - 9) Given the state-diagram of a stepper motor control function, design a logic circuit that complies with the depicted specs. Hint: Use two T-type FF(s), one input control signal "dir", and four output ports (23. 22. 21, 20) to generate the desired state output values T-FF. Transition Table d 0 1 0 dev T 0 HO 1 1 1 1 1 0 Assume states representation as: S0-00, S1-01, 52-10, 53-11 a) Complete the state-table (Marks-4-64 x 1/16) STATE-TABLE Input Fro Next Sule Medin B 0 0 0 0 T 0 T 0 0 1 I 1 0 0 T 0 1 1 1 0 1 T Mobile View ..? State A 0 D A T-4100 Ieput TB TA A Read Aloud 73 Ope Port 22 zi Headings ||

b) Find simplified logic equations for: TB: B'A BA BA BA BA M M ZI: M M 23: M' M BA B'A B'A B'A' B'A BA BA (Marks = 6x0.5) TA: M M ZO: M M 22: M' M B'A BA ВА' B'A' B'A BA BA B'A B'A B'A BA BA ||

7 of 12 c) Given the skeleton of the state-machine circuit, complete the schematic of the design by connecting multiplexers input ports to the right logic levels (0 or 1 as appropriate). (Marks = 2) X1 VCC Frequency 50Hz Ampude 2.5 2.5V Clock-Digital +25 XFGI $ [Etat VCC SV voc Clock voc UTA 7473 ww 1X45P 4.710 RO 25V VCC to USA 7473 74151 74151 RO 25V 25V TA 24 25V TB ||.