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It's LTspice
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It's LTspice
It's LTspice
Analog VLSI-Laboratory Laboratory #9: Analysis and Design of Two Stage Operational Amplifier with Miller Compensation Objective: To understand the fundamental operation of the two-stage operational amplifier with differential input and single ended output. Investigate how to compensate a two-stage operational amplifier by using the Miller technique. Simulate the operational amplifier using LTSpice and find out the key performance parameter. Fundamental Concepts: differential signal injection, current mirror, amplifier gain, pole and zero, frequency response, transient response, compensation, stability Task 1: Design a two-stage operational amplifier as given in Fig. 1 to meet the following requirement. We do not apply the compensation technique for now. A. DC gain: >70dB B. Gain Bandwidth: >100 MHz C. First stage and second stage load capacitance: 1pF Simulate the frequency response of this op-amp. Report the value of simulated DC gain, f_3dB, GBW (Gain Bandwidth Product), Unity-gain frequency, phase Margin. avdd M6 avdd M5 TestP TestPvcm p M7 Testp 11 M3 agnd ving TestN 0.2m TestN vinn V2 V3 vcm s 3.5 SINE(1.8) SINE(1.8) AC 0.50 AC 0.5 180 M2 TestN ac dec 21 1k 1G ;.op .model TestN nmos (kp-90u vt0-0.7 lambda=0.1) .model TestP pmos (kp=40u vt0=-0.7 lambda=0.1) Figure 1. Schematic of two stage operational amplifier 1. Provide the design procedure to meet the specifications above. Specify the dimension for all transistors. 2. Please verify the operation of the design in LTSpice. M1 TestN agnd M4 vout M8 TestN C2
Analog VLSI-Laboratory Laboratory #9: Analysis and Design of Two Stage Operational Amplifier with Miller Compensation Objective: To understand the fundamental operation of the two-stage operational amplifier with differential input and single ended output. Investigate how to compensate a two-stage operational amplifier by using the Miller technique. Simulate the operational amplifier using LTSpice and find out the key performance parameter. Fundamental Concepts: differential signal injection, current mirror, amplifier gain, pole and zero, frequency response, transient response, compensation, stability Task 1: Design a two-stage operational amplifier as given in Fig. 1 to meet the following requirement. We do not apply the compensation technique for now. A. DC gain: >70dB B. Gain Bandwidth: >100 MHz C. First stage and second stage load capacitance: 1pF Simulate the frequency response of this op-amp. Report the value of simulated DC gain, f_3dB, GBW (Gain Bandwidth Product), Unity-gain frequency, phase Margin. avdd M6 avdd M5 TestP TestPvcm p M7 Testp 11 M3 agnd ving TestN 0.2m TestN vinn V2 V3 vcm s 3.5 SINE(1.8) SINE(1.8) AC 0.50 AC 0.5 180 M2 TestN ac dec 21 1k 1G ;.op .model TestN nmos (kp-90u vt0-0.7 lambda=0.1) .model TestP pmos (kp=40u vt0=-0.7 lambda=0.1) Figure 1. Schematic of two stage operational amplifier 1. Provide the design procedure to meet the specifications above. Specify the dimension for all transistors. 2. Please verify the operation of the design in LTSpice. M1 TestN agnd M4 vout M8 TestN C2
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