MAC IP design (add and multiply) example 1. Design SIMD2 IP by modifying RTL code (submission of code) 2. Implement API

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answerhappygod
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MAC IP design (add and multiply) example 1. Design SIMD2 IP by modifying RTL code (submission of code) 2. Implement API

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MAC IP design (add and multiply)
example
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 1
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 1 (52.79 KiB) Viewed 44 times
1. Design SIMD2 IP by modifying RTL code (submission of
code)
2. Implement API (name is perform_simd1) for using SIMD2 IP
(submission of code)
3. Implementation of Application code implementing the example
presented (submission of code)
4. Simulation and verification of examples presented (submission of
waveform screen capture)
RTL code to modify with reference
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 2
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 2 (242.57 KiB) Viewed 44 times
API code to modify with reference / Application code to modify
with reference
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 3
Mac Ip Design Add And Multiply Example 1 Design Simd2 Ip By Modifying Rtl Code Submission Of Code 2 Implement Api 3 (148.21 KiB) Viewed 44 times
please help me ㅠㅠ
MAC IP 설계 (덧셈 후 곱셈) Core1 Memory 용 System interconnect SIMD2_IP 01 34 02 ? 04 + BB 05 ? 10 + 46 OA ? 38 1A 811 OC ?
1 include "ervp_global.vh" 2 3 module TEST1_APB 5 clk, 6 rstnn, 7 8 rpsel, 9 rpenable, 10 rpaddr, 11 rpwrite, 12 rpwdata, 13 rprdata, 14 rpready, rpslverr 15 16 ); 17 18 //////////////////////////// 19 / parameter input output */ 20 //////////////////////////// 21 22 parameter BW_ADDR = 1; 23 parameter BW_DATA = 1; 24 25 input wire clk, rstnn; 26 input wire rpsel; 27 input wire rpenable; 28 input wire [BW_ADDR-1:0] rpaddr; 29 input wire rpwrite; 30 input wire [BW_DATA-1:0] rpwdata; 31 output reg [BW_DATA-1:0] rprdata; 32 output wire rpready; 33 output reg rpslverr; 34 35 ///////////// 36 signals / 37 ///////////// 38 39 genvar 1; 40 41 wire [8-1:0] addr_offset=rpaddr; 42 reg is valid_addr; 43 44 reg [32-1:0] var_x, var_y, var_z; 45 reg we_x, we_y, we_z; 46 47 reg request_add; 48 reg request_sub; 49 reg request_mac; 50 55 always@(*) 56 begin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 end rprdata = 0; is_valid_addr = 0; we x = 0; we_y = 0; we_z = 0; request_add 0; request sub = 0; request_mac 0; if(rpsel-=1'b 1) begin end if(rpenable--1'b 1) begin end case (addr_offset) 8'h 0: begin end 8'h 4: begin end 8'h 8: begin end 8'h C: begin is_valid_addr = 1; rprdata var x; we_x rpwrite; is_valid_addr = 1; rprdata var_y; we y rpwrite; is_valid_addr = 1; rprdata var_z; we z rpwrite; is_valid_addr = 1; if(rpwrite--1'b 1) else endcase request_add 1; request sub 1; end 8'h 10: begin end default: is_valid_addr = 1; if(rpwrites=1'b 1) request_mac = 1; is_valid_addr = 0; 109 110 assign rpready = 1; 111 112 always@(posedge clk, negedge rstnn) 113 begin 114 if(rstnn==0) 115 var_x <= 0; 116 else if(we_x=-1'b 1) 117 var x < rpwdata; 118 end 119 120 always@(posedge clk, negedge rstnn) 121 begin 122 if(rstnn==0) 123 var y < 0; 124 else if(we_y=-1'b 1) 125 var y <= rpwdata; 126 end 127 128 always@(posedge clk, negedge rstnn) 129 begin 130 if(rstnn==0) var_z <= 0; 131 132 else if(we_z=-1'b 1) 133 var_z <= rpwdata; 134 else if(request_add) 135 var_z <= var_x + var_; 136 else if(request_sub) 137 var_z <= var_x - var_y; 138 else if(request_mac) 139 var_z <= (var_x var_y) + rpwdata; 140 end 141 142 always@(posedge clk, negedge rstnn) 143 begin. 144 if(rstnn==0) 145 rpslverr <= 0; 146 else if(rpsel=1'¹b 1) begin 147 148 149 150 151 152 end 153 end 154 155 endmodule 156 if(rpenable--1'b 0) rpslverr < 0; else rpslverr < ~is_valid_addr;
1 #include "platform_info.h" 2 #include "ervp_printf.h" 3 #include "ervp_reg_util.h" 4 5 #define OFFSET_X exe 6 #define OFFSET_Y 0x4 7 #define OFFSET Z 0x8 8 #define OFFSET_ADD exc #define OFFSET_SUB 0xC 10 #define OFFSET MAX 8x10 11 #define OFFSET_NOI_VALID 0x3 13 static inline unsigned int get_test1_addr (unsigned int offset) 14 { 15 return (I_TEST1_SLAVE_BASEADDR+offset); 16 17 18 void set_x(unsigned int value) 19 { 20 REG32(get_test1_addr (OFFSET_X)) = value; 21 } 22 23 unsigned int get_x() 24 { 25 return REG32(get_test1_addr (OFFSET_X)); 26 } 27 28 void set_y(unsigned int value) 29 ( 30 REG32(get_test1_addr (OFFSET_Y)) = value; 31 32 33 unsigned int get_y() 34 { 35 return REG32(get_test1_addr (OFFSET_Y)); 36 } 37 38 void set_z(unsigned int value) 39 { 40 REG32(get_test1_addr (OFFSET_Z)) value; 41 } 981 API 42 43 unsigned int get_z() 44 { 45 return REG32(get_test1_addr (OFFSET_Z)); 46} 47 48 49 void perform_add() 50 { 51 REG32(get_test1_addr (OFFSET_ADD)) = 0; 52 } 53 54 void perform_sub() 55 { 56 int temp; 57 temp = REG32(get_test1_addr (OFFSET_SUB)); 58} 59 60 void perform_mac() 61 { 62 REG32(get_test1_addr (OFFSET_MAX)) = 3; 63} 64 65 int main() { 66 set_x(3); 67 printf("\n%d", get_x()); set_y(6); printf("\n%d", get_y()); set_z(4); printf("\n%d", get_z()); perform_add(); printf("\n%d", get_z()); perform_sub(); printf("\n%d", get_z()); perform_mac(); printf("\n%d", get_z()); REG32(get_test1_addr (OFFSET_NOI_VALID)) = 0xffffffff; return 0; 68 69 70 71 72 73 HERRRR8 74 75 76 77 78 79 80 } API Application
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