The following sequential logic circuit is a latch. Its inputs are A & B, and its outputs are C and C’. C and C’ should o
Posted: Mon Jun 06, 2022 6:50 pm
The following sequential logic circuit is a latch.
Its inputs are A & B, and its outputs are C and C’. C and C’
should opposing values: C’= NOT(C).
a) Generate a truth table for the latch (hint: find a
known state that doesn’t depend on the previous output to begin
your analysis).
b) Generate a timing diagram for the latch (it should cover all
possibilities discussed in your truth table)
c) Can you identify any “actions” for this latch? Label them on
your truth table and timing diagram.
d) Compare this latch to the RS Latch; list their similarities
and differences
C' A B C
Its inputs are A & B, and its outputs are C and C’. C and C’
should opposing values: C’= NOT(C).
a) Generate a truth table for the latch (hint: find a
known state that doesn’t depend on the previous output to begin
your analysis).
b) Generate a timing diagram for the latch (it should cover all
possibilities discussed in your truth table)
c) Can you identify any “actions” for this latch? Label them on
your truth table and timing diagram.
d) Compare this latch to the RS Latch; list their similarities
and differences
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