Q1: (10 marks): Assume the following latencies for a single issue processor Instruction Using Result Another FP ALU op I

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Q1 10 Marks Assume The Following Latencies For A Single Issue Processor Instruction Using Result Another Fp Alu Op I 1 (37.34 KiB) Viewed 55 times

Q1: (10 marks): Assume the following latencies for a single issue processor Instruction Using Result Another FP ALU op Instruction Producing Result FP MUL/DIV FP ADD/SUB Load Double Another FP ALU op or Store Dobule Load Double FP ALU op Store Double Branch Int ADD 1 You are provided with 34 FP registers but you can only use even registers and any used register cannot be reused again for unrolling Schedule and unroll the following code a maximum number of times Write down the code and give clock cycles/Iteration for the following A) (4 marks] Unscheduled and without unrolling B) (0 marks) Scheduled and maximally unrolled LD FO, 0(4) LD F2, 003) // 14 carries a scalar constant / F12 carries a scalar constant DIV.D 16, 10, 14 SUBD F8, F2, F0 ADD.D F10, F8, F12 S.D F10, 084) S.D F8, 0(3) DADDR3, R3, DADDR4, 44 BNEQZ R4, Loop 02: (7.5+25 marks) Execute the following assembly code on a MIPS with a scoreboard and register the respective cycle number in the table Units available: FP MUL unit: 1 IP DIV unit: 1 FP ADD/SUB unit: 1 NT 2 Observe the following execution lengths for different execution units FP ADD/SUB 4 CC FP MUL 7 CC FP ON: 40 CC INTALU op: 1 CC LD/SD:2CC IS RO EXE WR Comments (Mention different hazards stalling the pipeline) MULD F8, F6, F2 DIV.D FR, F2, F4 SUBD F2, F8, F9 SD 12, 0(3) ADD D F1, F2, FIS LD $1,0(87) 02(b) (25 marks) Show how do the scoreboard status tables look like at the end of the clock cycle Functional Unit Status Table Number Name Buty Op FDs) Fi(Sect) Fle(Sec) QQ Register Status Table FO FI F2 F3 F4 FS FG F7 F8 F9 F10 F11 F12 F13 F14 15 Latency in Clock Cycles 1 0