1 of 2 CEN223 Term Project 1 Sequential Circuits Deadline: 09.05.2022 14:30 Lah, time 1. Analysis of a Synchronous Seque

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1 Of 2 Cen223 Term Project 1 Sequential Circuits Deadline 09 05 2022 14 30 Lah Time 1 Analysis Of A Synchronous Seque 1 (28.95 KiB) Viewed 17 times

1 of 2 CEN223 Term Project 1 Sequential Circuits Deadline: 09.05.2022 14:30 Lah, time 1. Analysis of a Synchronous Sequential Circuit (a) Analyse the synchronous sequential circuit of Fig. 1 by providing the state table and the finite state machine (FSM) diagram (b) Build this circuit in Logisim, connect a clock of frequency 1 Hz to the flip flops, connect two LEDs to the states of the flip flops and one LED to output y and show that the system goes through the states of the formed table with the corresponding output. A B B. Figure 1: A synchronous sequential circuit 2. Design of a Synchronous Sequential Circuit (a) A synchronous sequential circuit is to be designed that detects the overlapping patern "1001" in an input string (b) Draw the FSM diagram for this circuit 1 (c) Draw the state transition table using T flip flops (d) Work out input equations to T flip flops (e) Build the circuit in Logisim by connecting a clock and show that it works by providing an arbitrary overlapping input such as "110010010 and clock. The output should be I after receiving the 5th bit and 8th bit from left (the left most bit is the first bit received).