Problem 3 - Transmission Gate, Logical Effort Analysis Consider the following pass transistor based XOR gate. The inputs

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Problem 3 Transmission Gate Logical Effort Analysis Consider The Following Pass Transistor Based Xor Gate The Inputs 1 (107.64 KiB) Viewed 16 times

Problem 3 - Transmission Gate, Logical Effort Analysis Consider the following pass transistor based XOR gate. The inputs to the gate are driven by two unit sized inverters as shown in the figure. The gate drives a capacitance equivalent to 48 device widths at the output node Y. V ht hi ] 4 1 Figure 3 Determine the logical effort delay (d=gh+py) for the circuit for the following conditions: a) B = 0; A: 0-1 b) B = 1; A: 0-1 c) A = 0; B: 0 - 1 d) A = 1; B: 0 - 1 You can assume that Rpull-up for NMOS = 2* Rpuill-down for NMOS and Rpull-down for PMOS = 2* Rpull-up for PMOS. Assume y=1. Clearly state the assumptions that you make. Be sure to include effect of all capacitances. Based on the above analysis identify the critical path in the above XOR gate.