Write the verilog code for the load/ shift register in HDLBits. (1 point) b. Write the verilog code for the mod-N counte

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Write the verilog code for the load/ shift register in HDLBits. (1 point)
b. Write the verilog code for the mod-N counter in HDLBits. (1 point)
c. Write the verilog code for the top module in HDLBits, with one instance of the load/shift
register and one instance of the mod-N counter. (2 points)
module testbench (); reg Clk=0;
always #5 Clk = ~Clk; initial `probe_start; `probe(Clk);// A testbench reg Load = 1’b0; reg [4:0] D;wire [2:0] Q; initial begin// Create clock with period=10 // Start the timing diagram// Probe signal "Clk"// follow the given timing diagram#10 Load = 1’b1; D = 5’b10110; // apply a Load pulse#10 Load = 1’b0;#50; // run a few clock cycles$display ("Hello world! The current time is (%0d ps)", $time);#10 $finish; // Quit the simulation endtop DUT ( .Clk(Clk), .Load(Load), .D(D ), .Q(Q) ); // Sub-modules work too. endmodulemodule top (input Clk, input Load, input [4:0] D, output [2:0] Q); // declare internal wires// instantiate load/shift register // instantiate mod-N counter`probe(Load); // Sub-modules can also have `probe() `probe(D);`probe(Q);endmodule // top// module for load/shift register // module for mod-N counter
always #5 Clk = ~Clk; initial `probe_start; `probe(Clk);
// A testbench reg Load = 1’b0; reg [4:0] D;
wire [2:0] Q; initial begin
// Create clock with period=10 // Start the timing diagram
// Probe signal "Clk"
// follow the given timing diagram
#10 Load = 1’b1; D = 5’b10110; // apply a Load pulse
#10 Load = 1’b0;
#50; // run a few clock cycles
$display ("Hello world! The current time is (%0d ps)", $time);
#10 $finish; // Quit the simulation end
top DUT ( .Clk(Clk), .Load(Load), .D(D ), .Q(Q) ); // Sub-modules work too. endmodule
module top (input Clk, input Load, input [4:0] D, output [2:0] Q); // declare internal wires
// instantiate load/shift register // instantiate mod-N counter
`probe(Load); // Sub-modules can also have `probe() `probe(D);
`probe(Q);
endmodule // top
// module for load/shift register // module for mod-N counter

Write The Verilog Code For The Load Shift Register In Hdlbits 1 Point B Write The Verilog Code For The Mod N Counte 1 (52.84 KiB) Viewed 19 times

Ald Qout Problem 2–5 points in Part 1, you have encountered this circuit, where the serial output S. of a 5. bit load/shift register is used to enable a mod-N counter. When Load = 1, the register is loaded with the values on DA..Do while the counter is loaded with 0 (cleared). a. Write the verilog code for the load shift register in HDL Bits. (1 point) b. Write the verilog code for the mod-N counter in HDL Bits. (I point) c. Write the verilog code for the top module in HDL Bits, with one instance of the load shift register and one instance of the mod-N counter. (2 points) d. Run the simulation, using the following testbench template to help you start. Capture its waveform. (1 point) module testbench reg Cik- always #5 Cik-cik W Create clock with period 10 initial probe start: Start the timing diagram probe(Cik): Probe signal "CIK A testbench reg Load-1"bo; reg (4:01D wire [2:010 initial begin follow the given timing diagram #10 Load-1b1: D-5"b10110 il apply a Lead pulse #10 Load-1'60; #50; run a few clock cycles Sdisplay("Hello world! The current time is (%0dps1. Stime) Quit the simulation #10 Stinish: end top DUT CIK(Cik). LoadiLoad), DD).-010)% Sub-medules work too. endmodule module top (input Clk input Loud, input 14:0] D. output[2:010): // declare internal wires 1 instantiate load shift register il instantiate mod-N counter probelLoad): Sub-modules can also have probel) probe): probox: endmodule // top // module for load shift register module for mod-N counter