Design Specifications: Develop a VHDL realization of a Multi-Mode, parallel-in parallel-out, shift register that has fou

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Design Specifications Develop A Vhdl Realization Of A Multi Mode Parallel In Parallel Out Shift Register That Has Fou 1 (61.08 KiB) Viewed 22 times

Design Specifications: Develop a VHDL realization of a Multi-Mode, parallel-in parallel-out, shift register that has four mode of operation: Hold (00), Shift Right (01), Shift Left (10), and Parallel Load (11) in addition to the option of shifting the bits circularly or not. You will use Logisim as your primary simulation platform. As depicted below you have to include a discrete realization of the multi-mode shift register (given) for comparison and validation of your VHDL realization MultiMode Register PARALLELUT 40 Operation 30 d. 1 SR 10 L. 11 out CHER PARALLEL OUTPUT 5 ] PARALLELE Pre PALLE OVERUT O ED BR. 1. I Why VHDL? In previous quarters the development of a VHDL realization for your project design was optional. Even though a sizable bonus was offered not many students took advantage of that opportunity. Because of the importance of such topic in future courses we hope this project will help you to start familiarizing with VHDL