D4D3D2D1Do 101 10H Qoutputs Load 10 lod Of bit load/shftrols Load so mod-N counter Enable Q Load D4 D3 na CLK DI Do CU P

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D4d3d2d1do 101 10h Qoutputs Load 10 Lod Of Bit Load Shftrols Load So Mod N Counter Enable Q Load D4 D3 Na Clk Di Do Cu P 1 (92.41 KiB) Viewed 9 times

D4D3D2D1Do 101 10H Qoutputs Load 10 lod Of bit load/shftrols Load so mod-N counter Enable Q Load D4 D3 na CLK DI Do CU Problem 2–5 points All tied to os 0 In Part 1, you have encountered this X circuit, where the serial output S. of a 5- bit load/shift register is used to enable a mod-N counter. When Load = 1, the register is loaded with the values on DA..Do while the counter is loaded with 0 (cleared). a. Write the verilog code for the load/ shift register in HDLBits. (1 point) b. Write the verilog code for the mod-N counter in HDLBits. (1 point) c. Write the verilog code for the top module in HDLBits, with one instance of the load shift register and one instance of the mod-N counter. (2 points) d. Run the simulation, using the following testbench template to help you start. Capture its waveform. (1 point) module testbench 0; reg Clk=0; always #5 Cik = -Clk: Create clock with period=10 initial probe_start; // Start the timing diagram probe(Cik); // Probe signal "CIK" // A testbench reg Load = 100; reg (4:0) D: wire [2:01 Q: initial begin follow the given timing diagram #10 Load = 1'01; D = 5'610110; apply a Load pulse #10 Load = 100; #50: // run a few clock cycles $display ("Hello world! The current time is 0d ps)". Stime): #10 $finish; I Quit the simulation end top DUT(.Cik(Cik), Load(Load), D(D), QO); // Sub-modules work too. endmodule module top (input Clk, input Load, input [4:0] D, output [2:0] : // declare internal wires // instantiate load shift register // instantiate mod-N counter // Sub-modules can also have probe probe(Load); probe(D); probe(Q); endmodule // top module for load shift register module for mod-N counter