3 Section A 1. a) Find sum of products expressions for the functions f and f2 given by the circuit shown in Figure Qla u

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3 Section A 1. a) Find sum of products expressions for the functions f and f2 given by the circuit shown in Figure Qla using a BCD to decimal decoder, where w is the msh and z is the Isb. (You are not required to simplify the resultant expressions.) W D si X 4 to 10 line decoder 0 1 2 3 4 5 6 7 8 9 OOOOO y 12 Figure Qla 5 b) Design a circuit to implement the following function using an 8-to-1 multiplexer: f(D,C,B,A) = m(1,4,6,7,11,14) c) The Quine-McCluskey method is used to minimise the following Boolean expression: f(A,B,C,D,E) = m(13,15,22) + Şa(1,5,12,14,31) Where m represents the minterms for which must be true, and the terms following d are "don't care". The msb is A. Note: you are not required to perform the whole minimisation procedure; you only need to answer the following questions. Question continues overleaf.

Question continued. i) Identify and explain three mistakes in the Prime Implicant chart for the above problem, shown in Figure Qlci. (Note: the first column of the chart is correct.) (This column is correct.) 22 (1.5) (5.13) (15,31) (12,13,14,15) is 12 | 13 | 14 | 15 22 31 A.B.C.D.E X A'B'DE XX A'C.DE х х A.B.C.DE XX A'.B.C XXXX Figure Q1ci 5 ii) Write down your corrected Prime Implicant chart. Use it to find the Essential Prime Implicant(s), and the final minimum sum of products expression. Explain any decision(s) you have to make for the minimum sum of products. 8 d) Find the minimum sum of products expression for the function G given by the following Karnaugh map with map entered variables E and F. ab cd 00 01 11 10 00 EX 01 FX 11 1 1 Х 1 1 X 10 X1 E G Tata!

2. a) An ASM chart for a finite state machine is shown in Figure Q2a. 001 OUT2 010 T T F F OUT1 x х F F Y Y 100 x OUT2 Figure Q2a i) Design a PLA table to implement the logic of the present outputs and next states, for the ASM chart shown in Figure Q2a. Use the letters P, R and S as flipflop state variables, so that e.g. SRP=001 represents state A. Table headings are given below to help you begin: PLA inputs (Present state) (Present inputs) S R P X Y PLA outputs (Next state) (Present outputs) R p+ OUTI OUT2 S 5 ii) For the ASM chart shown in Figure Q2a, design simplified Boolean equations for the present outputs and next-state logic, assuming DFFs are used. A circuit diagram is not required. Question continues overleaf.

Question continued. b) You are asked to design a 16-bit adder circuit for a microprocessor, with the following design constraints (note that compound gates are not used): • The result (that is, the final sum) should be stable within one clock cycle The clock frequency is 40 MHz • The logic gates used each have a propagation delay of 2 ns The design is based around the l-bit adder circuit shown in Figure Q2b. A B TD Sum Cin Cout Figure Q2b 5 1) Explain, including calculations, why neither a serial adder, nor a parallel "ripple carry' adder, could satisfy the constraints above. 10 ii) Explain how a 'carry look-ahead adder" (CLA) design using four 4-bit CLA blocks could satisfy the specific constraints above. Include relevant equations and calculations; you may also include a circuit diagram(s) to support your explanation. Hints: Start by calculating the maximum delay from Co to Sum (where Co is the carry-in to the whole circuit) across a 4-bit adder block using propagate generate and carry look- ahead logic. This should come to 8 ns (you will need to explain why). Secondly, extend your design to 16-bit addition using group propagate generate and a further layer of CLA logic. Assume that all gates, including XOR, have a delay of 2 ns. a Total 25

3. a) Given the following Assembly language program for the ARM Cortex MO using a little endian configuration: AREA asm prog, CODE, READONLY THUMB EXPORT start start PROC ; Start of the program 0x00004004 LDR TO, =0x00010000 0x00004006 LDR r1, -0x5CB6B32F 0x00004008 LDR 12, =0x3D2D7B4B 0x0000400A LDR 13, =0xF100F 100 0x0000400C LDR r4, =0x88011022 i) 0x00004014 ADDS r1, r1, 12 ii) 0x00004016 BICS 12, r3 iii) 0x00004018 ASRS r3, ro, #0x04 iv) Ox0000401A STRH r4, [ro] ENDP END End of the program Assuming that register r15 initially holds the value 0x00004004, find the values held in registers t1, 12, 13 and in the memory after the instructions (1) to (iv) are executed. For each executed instruction you are required to provide: • the procedure to calculate the result value after the instruction is executed. • the status of the modified register(s) after the execution of the instruction. • the status of the memory, only if it changes. 2 3 2 5 Question continues overleaf.

Question continued. 2 2 2 b) The 32-bit two's complement number OxFFFFF81B is stored in one of the ARM Cortex MO registers. What is its decimal representation? c) Find the IEEE 754 floating point format (single precision) for the decimal numbers: i) 415.510 ii) +41.310. d) Find the decimal number that is equivalent to OxC4610000 in the IEEE 754 floating point format e) Find the 32 bit two's complement format for the decimal numbers: i) -1910 ii) -1,919,191,91910. (Note that 0x72648B6F is the hexadecimal equivalent of +1,919,191,91910.) 3 N 2 2 Total 25