Some portion of cache system B represented a 2-way set-associative mapping cache system The system is byte-addressable a

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Some Portion Of Cache System B Represented A 2 Way Set Associative Mapping Cache System The System Is Byte Addressable A 1 (44.57 KiB) Viewed 61 times

Some portion of cache system B represented a 2-way set-associative mapping cache system The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag set Number Word within black 100 101 110 111 10 1000 0100 10010110 11012016111102110 111100 0100 10010110 1101 2212721c2..p2e 10 1000 0100 10010110 111012462412 111100 0100 11010110 1110 521.926821002 10 1000 0100 10010110 11112044611.01:2510 111100 0100 10010110 11113210 7210 C21.02 10 1000 0100 10010111 0000421621061161210 111100 010011010111 0000 520125216 52: 10 1000 0100 10010111 0001 2716611 130211 111100 0100 1001011100012212721c21824 10 1000 0100 10010111 0010 |A282104110A2.. 1111000100 11010111 0010 5216221, 5210 52: 1. What is the size of the main memory for cache system B? 2. What is the size of cache memory? 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read? 5. If we access memory as the following order in cache system B: A1 FFBB B1 FF BB A1 FF BB B1 FF BB A1 FFBB B1 FF BB how many cache misses would occur for the data request?