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- Could You Please Solve And Write All The Questions In Detail 1 (228.71 KiB) Viewed 40 times
Could you please solve and write all the questions in detail?
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answerhappygod
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Could you please solve and write all the questions in detail?
Could you please solve and write all the questions in
detail?
HW#5 5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Offset Tag 63-10 Index 9-5 4-0 5.5.1 [5] <$5.3> What is the cache block size (in words)? 5.5.2 [5] <$5.3> How many blocks does the cache have? 5.5.3 [5] <$5.3> What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Hex Dec 00 0 04 4 10 16 84 132 Address E8 АО 400 232 160 1024 1E 30 8C C1C B4 884 140 3100 180 2180 5.5.4 [20] <$5.3> For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). 5.5.5 [5] <$5.3> What is the hit ratio? 5.5.6 (5] <$5.3> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. For example, <0, 3. Mem[OxC00] -Mem[OxC1F]> 5.7 Consider the following program and cache behaviors. Data Reads per Data Writes per Instruction Cache Data Cache 1000 Instructions 1000 Instructions Miss Rate Miss Rate 250 100 0.30% 2% Block Size (bytes) 64 5.7.1 [10] <$95.3, 5.8> Suppose a CPU with a write-through, write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? (Assume each miss generates a request for one block.) 5.7.2 [10] <S$5.3, 5.8> For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2? 5.13 Mean time between failures (MTBF), mean time to replacement (MTTR), and mean time to failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the questions about a device with the following metrics: MTTF MTTR 1 Day 3 Years 5.13.1 [5] <$5.5> Calculate the MTBF for such a device. 5.13.2 [5] <$5.5> Calculate the availability for such a device. 5.13.3 [5] <$5.5> What happens to availability as the MTTR approaches 0? Is this a realistic situation? 5.13.4 (5] <$5.5> What happens to availability as the MTTR gets very high, i.e., a device is difficult to repair? Does this imply the device has low availability? 5.17 There are several parameters that affect the overall size of the page table. Listed below are key page table parameters. Virtual Address Size Page Size Page Table Entry Size 32 bits 8 KiB 8 4 bytes 5.17.1 [5] <$5.7> Given the parameters shown above, calculate the maximum possible page table size for a system running five processes. 5.17.2 [10] <$5.7> Given the parameters shown above, calculate the total page table size for a system running five applications that each utilize half of the virtual memory available, given a two-level page table approach with up to 256 entries at the 1"' level. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amount of memory required for this page table. 5.17.3 [10] <$5.7> A cache designer wants to increase the size of a 4 KiB virtually indexed, physically tagged cache. Given the page size shown above, is it possible to make a 16 KiB direct-mapped cache, assuming two 64-bit words per block? How would the designer increase the data size of the cache? 5.19 The following table shows the contents of a four-entry TLB. Entry-ID Valld VA Page Modified Protection PA Page 1 1 140 1 RW 30 2 RX 34 200 RO 32 1 280 RW 31 1 0 40 0 0 3 1 1 4 0 5.19.1 [5] <$5.7> Under what scenarios would entry 3's valid bit be set to zero? 5.19.2 [5] <$5.7> What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? 5.19.3 [5] <$5.7> What happens when an instruction writes to VA page 200?
detail?
HW#5 5.5 For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Offset Tag 63-10 Index 9-5 4-0 5.5.1 [5] <$5.3> What is the cache block size (in words)? 5.5.2 [5] <$5.3> How many blocks does the cache have? 5.5.3 [5] <$5.3> What is the ratio between total bits required for such a cache implementation over the data storage bits? Beginning from power on, the following byte-addressed cache references are recorded. Hex Dec 00 0 04 4 10 16 84 132 Address E8 АО 400 232 160 1024 1E 30 8C C1C B4 884 140 3100 180 2180 5.5.4 [20] <$5.3> For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and (3) which bytes were replaced (if any). 5.5.5 [5] <$5.3> What is the hit ratio? 5.5.6 (5] <$5.3> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. For example, <0, 3. Mem[OxC00] -Mem[OxC1F]> 5.7 Consider the following program and cache behaviors. Data Reads per Data Writes per Instruction Cache Data Cache 1000 Instructions 1000 Instructions Miss Rate Miss Rate 250 100 0.30% 2% Block Size (bytes) 64 5.7.1 [10] <$95.3, 5.8> Suppose a CPU with a write-through, write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? (Assume each miss generates a request for one block.) 5.7.2 [10] <S$5.3, 5.8> For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2? 5.13 Mean time between failures (MTBF), mean time to replacement (MTTR), and mean time to failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the questions about a device with the following metrics: MTTF MTTR 1 Day 3 Years 5.13.1 [5] <$5.5> Calculate the MTBF for such a device. 5.13.2 [5] <$5.5> Calculate the availability for such a device. 5.13.3 [5] <$5.5> What happens to availability as the MTTR approaches 0? Is this a realistic situation? 5.13.4 (5] <$5.5> What happens to availability as the MTTR gets very high, i.e., a device is difficult to repair? Does this imply the device has low availability? 5.17 There are several parameters that affect the overall size of the page table. Listed below are key page table parameters. Virtual Address Size Page Size Page Table Entry Size 32 bits 8 KiB 8 4 bytes 5.17.1 [5] <$5.7> Given the parameters shown above, calculate the maximum possible page table size for a system running five processes. 5.17.2 [10] <$5.7> Given the parameters shown above, calculate the total page table size for a system running five applications that each utilize half of the virtual memory available, given a two-level page table approach with up to 256 entries at the 1"' level. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amount of memory required for this page table. 5.17.3 [10] <$5.7> A cache designer wants to increase the size of a 4 KiB virtually indexed, physically tagged cache. Given the page size shown above, is it possible to make a 16 KiB direct-mapped cache, assuming two 64-bit words per block? How would the designer increase the data size of the cache? 5.19 The following table shows the contents of a four-entry TLB. Entry-ID Valld VA Page Modified Protection PA Page 1 1 140 1 RW 30 2 RX 34 200 RO 32 1 280 RW 31 1 0 40 0 0 3 1 1 4 0 5.19.1 [5] <$5.7> Under what scenarios would entry 3's valid bit be set to zero? 5.19.2 [5] <$5.7> What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? 5.19.3 [5] <$5.7> What happens when an instruction writes to VA page 200?