5.7 Consider the following program and cache behaviors. Data Reads per Data Writes per Instruction Cache Data Cache 1000

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5 7 Consider The Following Program And Cache Behaviors Data Reads Per Data Writes Per Instruction Cache Data Cache 1000 1 (30.11 KiB) Viewed 46 times

5.7 Consider the following program and cache behaviors. Data Reads per Data Writes per Instruction Cache Data Cache 1000 Instructions 1000 Instructions Miss Rate Miss Rate 250 100 0.30% 2% Block Size (bytes) 64 5.7.1 [10] <895.3, 5.8> Suppose a CPU with a write-through, write-allocate cache achieves a CPI of 2. What are the read and write bandwidths (measured by bytes per cycle) between RAM and the cache? (Assume each miss generates a request for one block.) 5.7.2 [10] <S$5.3, 5.8> For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the read and write bandwidths needed for a CPI of 2?