Design, Registers and Counters
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Digital Logic Design, Sequential Circuit Analysis and Design, Registers and Counters
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Digital Logic Design, Sequential Circuit Analysis and Design, Registers and Counters
Digital Logic Design, Sequential Circuit Analysis and
Design, Registers and Counters
COE 202 Digital Logle Design It is required to design a synchronous sequential circuit that receives a serial inprat X that produces 1 when the input sequence is either {0111) or (1100) assuming no overlapping sequences. The output Z is also a bit stream at produces a 1 only after detecting any of the two sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state, Example Clock cycle 2 ) 10 11 12 13 14 11! 0 U 11 0 0 0 0 1 0 0 0 0 0 1 0 0 0 a) (10 pouts) Draw a Mealy state diagram of the sequential circuit b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Specify the K maps and write the minimal next state and output equations. c) (10 points) Write a struetural Verilog model that model your implemented sequential circuit by modeling the Flip-Figs and smalm them and modeling the comisional patung eithia assign statement or galetes. d) (10 points) Wille behavioral Verile description is models you slate chap:n pal () e) (10 points) Write a test bench that tests BOTH tise structural Verilog model of part (c) and the bebaul Veulog model of pant (a) ustg the example mput sequence shown above. Call the outpats 21 and Z2 for the models in (c) and (d), respectively. Staat by resetting all flip-flops and then apply the input sequence of X. Verify that your circuit produces the correct output by including the generated waveform from simulation and comparing to the given example above Submit a report Word or PDF document) that should contain: The state diagram of your design (part a i The state table K-map and logic equations of your sequential carcit (part b) 1. A copy of the Valog modules and test benches of pants (e), (d), zod (). 1. The tumang cangrams (waveforms) taken durectly as suapslots from the sumulator for parts (e) and analysis of output The assignment is solved individually. Submut a soft copy of the report on Blackboard and hard copy in the box outside my office (22 203).
Design, Registers and Counters
COE 202 Digital Logle Design It is required to design a synchronous sequential circuit that receives a serial inprat X that produces 1 when the input sequence is either {0111) or (1100) assuming no overlapping sequences. The output Z is also a bit stream at produces a 1 only after detecting any of the two sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state, Example Clock cycle 2 ) 10 11 12 13 14 11! 0 U 11 0 0 0 0 1 0 0 0 0 0 1 0 0 0 a) (10 pouts) Draw a Mealy state diagram of the sequential circuit b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Specify the K maps and write the minimal next state and output equations. c) (10 points) Write a struetural Verilog model that model your implemented sequential circuit by modeling the Flip-Figs and smalm them and modeling the comisional patung eithia assign statement or galetes. d) (10 points) Wille behavioral Verile description is models you slate chap:n pal () e) (10 points) Write a test bench that tests BOTH tise structural Verilog model of part (c) and the bebaul Veulog model of pant (a) ustg the example mput sequence shown above. Call the outpats 21 and Z2 for the models in (c) and (d), respectively. Staat by resetting all flip-flops and then apply the input sequence of X. Verify that your circuit produces the correct output by including the generated waveform from simulation and comparing to the given example above Submit a report Word or PDF document) that should contain: The state diagram of your design (part a i The state table K-map and logic equations of your sequential carcit (part b) 1. A copy of the Valog modules and test benches of pants (e), (d), zod (). 1. The tumang cangrams (waveforms) taken durectly as suapslots from the sumulator for parts (e) and analysis of output The assignment is solved individually. Submut a soft copy of the report on Blackboard and hard copy in the box outside my office (22 203).