It is required to design a synchronous sequential circuit that receives a serial input X that produces 1 when the input

Business, Finance, Economics, Accounting, Operations Management, Computer Science, Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Algebra, Precalculus, Statistics and Probabilty, Advanced Math, Physics, Chemistry, Biology, Nursing, Psychology, Certifications, Tests, Prep, and more.
Post Reply
answerhappygod
Site Admin
Posts: 899603
Joined: Mon Aug 02, 2021 8:13 am

It is required to design a synchronous sequential circuit that receives a serial input X that produces 1 when the input

Post by answerhappygod »

It Is Required To Design A Synchronous Sequential Circuit That Receives A Serial Input X That Produces 1 When The Input 1
It Is Required To Design A Synchronous Sequential Circuit That Receives A Serial Input X That Produces 1 When The Input 1 (179.36 KiB) Viewed 57 times
please solve it using my sequence
It is required to design a synchronous sequential circuit that receives a serial input X that produces 1 when the input sequence is either {0111} or {1100; assuming no overlapping sequences. The output Z is also a bit stream that produces a 1 only after detecting any of the two sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state. Example: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Clock cycle X Z 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 a) (10 points) Draw a Mealy state diagram of the sequential circuit. b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Specify the K-maps and write the minimal next state and output equations. c) (10 points) Write a structural Verilog model that models your implemented sequential circuit by modeling the D Flip-Flops and instantiating them and modeling the combinational part using either assign statement or gate primitives. d) (10 points) Write a behavioral Verilog description that models your state diagram in part (a). e) (10 points) Write a test bench that tests BOTH the structural Verilog model of part (c) and the behavioral Verilog model of part (d) using the example input sequence shown above. Call the outputs Z1 and Z2 for the models in (C) and (d), respectively. Start by resetting all flip-flops and then apply the input sequence of X. Verify that your circuit produces the correct output by including the generated waveform from simulation and comparing to the given example above. f) Submit a report (Word or PDF document) that should contain: i. The state diagram of your design (part a). ii. The state table, K-maps, and logic equations of your sequential circuit (part b). iii. A copy of the Verilog modules and test benches of parts (c), (d), and (e). The timing diagrams (waveforms) taken directly as snapshots from the simulator for parts (e) and analysis of output. The assignment is solved individually. Submit a soft copy of the report on Blackboard and hard copy in the box outside my office (22-203). iv.
Join a community of subject matter experts. Register for FREE to view solutions, replies, and use search function. Request answer by replying!
Post Reply