(5 points) Consider the execution of the following sequence of instructions on the five-stage pipelined processor: Suppo

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(5 points) Consider the execution of the following sequence of
instructions on the five-stage pipelined processor:
Suppose the third instruction is detected to have an invalid
target address and cause an exception in the ID stage (i.e., in
clock cycle 4). What instructions will appear in the IF, ID, EX,
MEM, and WB stages, respectively, in clock cycle 5? Note that each
instruction in your answer should be one chosen from the given
instructions, the NOP instruction (or bubble), and the first
instruction of the exception handler.