. 1 ACLOAD PCLOAD + PCINC 1 8 MPU AC PC 1 PCBUST ACINC READ 1 8 ADD / SUB/ AND / OR ALUSEL1 ALUSELO ! ALUBUS 1 RD 8 Memo

[answerhappygod]

1 Acload Pcload Pcinc 1 8 Mpu Ac Pc 1 Pcbust Acinc Read 1 8 Add Sub And Or Alusel1 Aluselo Alubus 1 Rd 8 Memo 1 (134.67 KiB) Viewed 106 times

1. What is the optimum size of the memory?
2. What is the size of the state decoder?
2 x 4
3 x 8
4 x 16
5 x 32
6 x 64
3. Which of the following is the correct input to the state
counter?
"0, IR[2:0]"
"1, IR[2:0]"
"IR[2:0], 0"
"IR[2], 0, IR[1:0]"
4. What state/s should activate the CLR control line of the
state counter?
5. What state/s should activate the INC control line of the
state counter?
6. What state/s should activate the LD control line of the
state counter?
7. What control signals are active during FETCH1?
8. What control signals are active during the first execute
cycle of XOR instruction.
9.What control signals are active during the execute cycle of INC
instruction?
10. What state/s will activate the control signal
DRLOAD?
11. What state/s will activate the control signal
ALUBUS?
12. What state/s will activate the control signal
MEMBUS?
13. "At what decoder output should JMP1 be connected? (just
use a numerical value for your answer i.e. 1, 2, 30)"
14. "At what decoder output should INC1 be connected? (just
use a numerical value for your answer i.e. 1, 2, 30)"
15. "At what decoder output should XOR2 be connected? (just
use a numerical value for your answer i.e. 1, 2, 30)"
. 1 ACLOAD PCLOAD + PCINC 1 8 MPU AC PC 1 PCBUST ACINC READ 1 8 ADD / SUB/ AND / OR ALUSEL1 ALUSELO ! ALUBUS 1 RD 8 Memory 8-bit BUS -DRLOAD bo 8 DR -DRBUS 5 AR Control Signals MEMBUS ARLOAD 3 IR 五 3 Control Unit IRLOAD 1 ALU OPERATIONS SELECT LINES / CONTROL SIGNALS ALU OPERATION ALUSEL1 ALUSELO XOR 0 0 SUB 1 0 ADD 1 1 INSTRUCTION SET ARCHITECTURE Each instruction code is composed of eight bits. Bits 7-5 are used for the opcodes, while bits 4-0 are for the address. Instruction Instruction XOR Opcode 010 Instruction Format 010 AAAAA Opcode 101 Instruction Format 101 AAAAA JMP SUB 011AAAAA LDA 110 110 AAAAA 011 100 ADD 100 AAAAA INC 111 111 XXXXX FETCH AND EXECUTE CYCLES (RTL) FETCH CYCLE XOR EXECUTE CYCLE ADD EXECUTE CYCLE ADD1 DR MEM FETCH1 AR PC XOR1 DR MEM ADD2 AC AC + DR FETCH2 FETCH3 XOR 2 AC AC DR INC EXECUTE CYCLE SUB EXECUTE CYCLE DR MEM, IR DR[7:5), AR DR[4:0) PC PC + 1 INC1 AC AC + 1 SUB1 DR MEM SUB2 AC AC - DR JMP EXECUTE CYCLE JMP1 PC DR[4:0) LDA EXECUTE CYCLE LDA1 DR MEM LDA2 AC DR